Rocketick Technologies Ltd

Broadcom Corporation

Uri Tal

Shay Mizrachi

Tomer Ben-David

Caitlin Bestler

Rafi Shalom

Eliezer Aloni

Amit Oren

Dov Hirshfeld

Kobby Carmona

Ishay Geller

Ido Kasher

Merav Sicron

Eliezer Tamir

Kan (Frankie) Fan

Ronen Gal

Uri Elzur

Scott Sterling McDaniel

Steven B Lindsay

Mcrav Sicron

Hav Khauv

A method for design simulation includes partitioning a verification task of a design () into a first plurality of atomic Processing Elements (PEs&#x2014;) having execution dependencies (), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (), which includes a second plurality of processors () operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.

Simulation using parallel processors

A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.

Efficient parallel computation of dependency problems

A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks.

Parallel simulation using multiple co-simulators

A method for design simulation includes partitioning a verification task of a design () into a first plurality of atomic Processing Elements (PEs-) having execution dependencies (), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (), which includes a second plurality of processors () operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.

A method for design simulation includes partitioning a verification task of a design into a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device, which includes a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.

Certain aspects of a method and system for configuring a plurality of network interfaces that share a physical interface (PHY) may include a system comprising one or more physical network interface controllers (NICs) and two or more virtual NICs. One or more drivers associated with each of the virtual NICs that share one or more Ethernet ports associated with the physical NICs may be synchronized based on controlling one or more parameters associated with one or more Ethernet ports. One or more wake on LAN (WoL) patterns associated with each of the drivers may be detected at one or more Ethernet ports. A wake up signal may be communicated to one or more drivers associated with the detected WoL patterns. One of the drivers may be appointed to be a port master driver. If a failure of the appointed port master driver is detected, another driver may be appointed to be the port master driver.

Method and system for configuring a plurality of network interfaces that share a physical interface

A computing method includes accepting a definition of a computing task (), which includes multiple atomic Processing Elements (PEs&#x2014;) having execution dependencies (). Each execution dependency specifies that a respective first PE is to be executed before a respective second PE. The computing task is compiled for concurrent execution on a multiprocessor device (), which includes multiple processors () that are capable of executing a first number of the PEs simultaneously, by arranging the PEs, without violating the execution dependencies, in an invocation data structure () including a second number of execution sequences () that is greater than one but does not exceed the first number. The multiprocessor device is invoked to run software code that executes the execution sequences in parallel responsively to the invocation data structure, so as to produce a result of the computing task.

A network interface device for use with a host computer that includes a host processor and a memory, and which is configured to concurrently run a master operating system and at least one virtual operating system. The device includes a bus interface that communicates over a bus with the host processor and the memory, and a network interface, which is coupled to send and receive data packets carrying data over a packet network. A protocol processor is coupled between the bus interface and the network interface so as to convey the data between the network interface and the memory while performing protocol processing on the data packets under instructions from the at least one virtual operating system, while bypassing the master operating system.

Network interface device serving multiple host operating systems

A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network interface and the memory via the bus interface while performing protocol offload processing on the data packets in accordance with multiple different application flows. The bus interface queues the data for transmission over the bus in a plurality of queues that are respectively assigned to the different application flows, and transmits the data over the bus according to the queues.

Network interface device with flow-oriented bus interface

A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface, including at least first and second physical ports, which are coupled to send and receive data packets carrying data over a packet network. A protocol processor includes a single transmit processing pipeline and a single receive processing pipeline, which are coupled between the bus interface and the network interface so as to convey the data between both of the first and second physical ports of the network interface and the memory via the bus interface while performing protocol offload processing on the data packets.

Multi-port network interface device with shared processing resources

A method for communication includes inputting from a host processor to a network interface device a sequence of work requests indicative of operations to be carried out by the network interface device with respect to a plurality of the connections. The device looks ahead through the sequence in order to identify at least first and second operations that are to be carried out with respect to one of the connections in response to first and second work requests, respectively, wherein the second work request does not immediately follow the first work request in the sequence. The device loads the context data for the one of the connections from a host memory into a context cache, and performs at least the first and second operations sequentially while the context data are held in the cache.

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Netanya, Israel

Uri Tal