Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Marvell Israel (misl) Ltd.

Uri Dayan

Idan Rozenberg

Moshe Anschel

Itzhak Barak

Itay S Peled

Yuval Peled

Doron Schupper

Jacob Efrat

Zvika Rozenshein

Brett L Lindsley

Avraham Horn

Moshe Tarrab

Dan Ilan

Erez Steinberg

Kostantin Godin

Erez Arbel-Meirovich

Aviram Amir

Ron Shaposhnikov

Jacob Tokar

Moshe Bachar

Amir Paran

Itzhaki Barak

Yoram Salant

Amir Kleen

Dvir Rune R Peleg

Guy Shumeli

Shahar Nahum

Liron Artsi

Joe Paul Gergen

A data processing device for executing a program is described. The program comprises one or more instruction groups and one or more predicates, each instruction group comprising one or more instructions. The data processing device comprises a processing unit and a trace unit connected to or integrated in the processing unit. The trace unit generates a predicate trace for tracing the values of the one or more predicates. The processing unit executes, in each of a series of execution periods, one of the instruction groups and updated the values of none, one, or more of the predicates in dependence on the respective instruction group. The trace unit appends the updated values of the none, one, or more predicates to the predicate trace and does not append any non-updated values of the predicates. A method of reporting predicate values and a data carrier are also disclosed.

Device and method for tracing updated predicate values

A network device and method for packet processing are provided. A packet processing accelerator is configured to receive packets from a network and define for ones of the packets a data unit corresponding to the packet. The packet processing accelerator is configured to perform a first set of packet processing operations on the data unit. A central processing unit (CPU) is configured to perform a second set of packet processing operations on the data unit. A buffer is configured to pass data units from the packet processing accelerator to the CPU, and vice versa, where the buffer is configured to store data units in one or more lines of the buffer. Dummy data units fill a space in a buffer line that is not occupied by a data unit, and the dummy data units include an indication that the space occupied by the dummy data units is an empty space.

Network device and method for packet processing

A processor system is adapted to carry out a predicate swap instruction of an instruction set to swap, via a data pathway, predicate data in a first predicate data location of a predicate register with data in a corresponding additional predicate data location of a first additional predicate data container and to swap, via a data pathway, predicate data in a second predicate storage location of the predicate register with data in a corresponding additional predicate data location in a second additional predicate data container.

Processor system with predicate register, computer system, method for managing predicates and computer program product

A method for managing branch instructions, the method includes: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instruction during a single execution cycle; receiving, at a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages, each pipeline stage that generates an instruction fetch request stores a variable length group of instructions that comprises a branch instruction; sending to the fetch unit an instruction fetch command that is responsive to a first in order branch instruction in the pipeline stages; wherein if the first in order fetch command is a conditional fetch command then the instruction fetch command comprises a resolved target address; wherein the sending of the instruction fetch command is restricted to a single instruction fetch command per a single execution cycle.

Method for managing branch instructions and a device having branch instruction management capabilities

A method for executing an instruction, the method includes: executing a compare and configure mask instruction, wherein the executing comprises: performing a comparison to provide a comparison result; and configuring, in response to the comparison result, a multiple bit mask that is stored in a multiple-purpose register; wherein all bits of the multiple bit mask are configured to have the same value; and applying an algorithmic operation on the multiple bit mask to provide an algorithmic operation result; wherein the algorithmic operation result represents an outcome of a high level programming language conditional statement.

System, method and computer program product for executing a high level programming language conditional statement

A system and method for modifying an information unit, the method includes the following stages: (i) receiving, over a first bus, a request to initiate a snooping type atomic operation associated with at least one information unit located at a first address of a memory module; (ii) providing the information unit over the first bus; (iii) attempting to complete the snooping type atomic operation of an updated information unit; and (iv) defining the atomic operation as a failed atomic operation if during at least one stage of receiving, providing and attempting, the first address was locked as a result of a locking type atomic operation.

Method and apparatus for modifying an information unit using an atomic operation

A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.

Method for speculative execution of instructions and a device having speculative execution capabilities

A memory management unit that includes: (i) multiple data segment descriptors, each data segment descriptor associated with a data memory segment; (ii) multiple program segment descriptors, each program segment descriptor associated with a program memory segment; and (iii) a controller, adapted to replace the content of the multiple data segment descriptors and the multiple program segment descriptors in response to a task switch. A method for memory management, the method includes: (i) providing multiple data segment descriptors; each data segment descriptor associated with a data memory segment, and providing multiple program segment descriptors, each program segment descriptor associated with a program memory segment; (ii) receiving and storing a program task identifier and a data task identifier; (iii) receiving a data access request and determining how to handle the data access request in response to a content of the multiple data segment descriptors; and (iv) receiving a program access request and determining how to handle the program access request in response to a content of the multiple program segment descriptors.

Descriptor-based memory management unit and method for memory management

A method and apparatus non-intrusive tracing. The method includes: counting selected events by multiple counters; sampling the multiple counters to retrieve multiple counter values in response to predefined triggering events; receiving additional trace information that comprises at least one program counter value, and outputting, as a trace information, at least one of the multiple counters values and the additional trace information.

Method and apparatus for non-intrusive tracing

A system for instructing a data processor, the system including an instruction root having an operation selection field for selecting an operation to be performed by said data processor and an instruction prefix. The instruction prefix has a field selected from the group of a conditional execution field for selecting a condition under which a data processor will perform said selected operation, an operand length modification field for modifying the selected operation so as to be performed on an operand having a different length, an instruction group field for selecting a length of an instruction group that includes the instruction root, and a prefix length selection field for selecting a length of said instruction prefix. A data processor system responsive to this instruction system is also disclosed. An instruction system for statically grouping instructions without using an instruction prefix is also disclosed.

Data processor instruction system for grouping instructions with or without a common prefix and data processing system that uses two or more instruction grouping methods

The present invention provides a task scheduling accelerating method, device and article of manufacture for determining and controlling multi-tasking. The device includes a synchronous task command interface for receiving commands from tasks on the host processor; an asynchronous task command interface for receiving commands from tasks and interrupt service routines on the host processor; an interrupt service routine interface for specifying and controlling a task switch; a semaphore post queue interface for specifying and determining a status of a data queue stored in the host processor; a status register for specifying a status of the task scheduling accelerator device; a computational unit for computing task scheduling decisions; and a bus for moving data between registers/interfaces and the computational unit.

Method, device and article of manufacture for implementing a real-time task scheduling accelerator

Growing community of inventors

Herzelia, Israel

Uri Dayan