Intel Corporation

Commex Technologies, Ltd.

Uri C Weiser

Edward Thomas Grochowski

Avraham Ganor

Yaron Shachar

Yehiel Engel

Tal Horowitz

Michael Chaim Schnarch

Donald B Alpert

Jack D Mills

Hong Wang

Gad Shlomo Sheaffer

Alexander D Peleg

Ron Gabor

Yaakov Yaari

Kenneth D Shoemaker

Doron Orenstein

Avi Mendelson

David Perlmutter

The present invention provides an improved platform hub that aims to, in some embodiments, optimize system resources to improve system performance and/or reduce consumption of power.

Systems and methods for efficient handling of data traffic and processing within a processing device

Disclosed are embodiments of a system, methods and mechanism for using idle thread units to perform acceleration threads that are transparent to the operating system. When the operating system scheduler has no work to schedule on the idle thread units, the operating system may issue a halt or monitor/mwait or other instruction to place the thread unit into an idle state. While the thread unit is idle, from the operating system perspective, the thread unit may be utilized to perform speculative acceleration threads in order to accelerate threads running on non-idle thread units. The context of the idle thread unit is saved prior to execution of the acceleration thread and is restored when the operating system requires use of the thread unit. The acceleration threads are transparent to the operating system. Other embodiments are also described and claimed.

Acceleration threads on idle OS-visible thread execution units

An apparatus and method for improving the performance of superscalar pipelined computers using branch prediction and verification that the predicted branch is correct. A predicted branch may be resolved in one of two distinct pipeline stages, and a method is provided for handling branches that are resolved in either of the pipeline stages. A branch verification method is provided that verifies that the architecturally correct instructions are in the decode and execution stages. Furthermore, two sets of prefetch buffers are provided to allow branch prediction when multiple clock decoding is required by a multi-clock instruction.

Branch prediction and resolution apparatus for a superscalar computer

The specification discloses a method and apparatus for determining the length of variable-length instructions that appear sequentially in an instruction stream without differentiation. The apparatus may be used to facilitate parallel processing of such variable-length instructions by a computer system. The apparatus includes: a circuit for providing a boundary marker for each instruction to indicate a boundary between that instruction and another instruction in the instruction stream, a circuit for processing instructions in sequence, a circuit for determining an actual boundary of a first instruction as it is processed, a circuit for comparing the boundary marker and the actual boundary of the first instruction to determine whether they match, a circuit for updating the boundary marker of the first instruction to the actual boundary of the first instruction when the boundary value and the actual boundary of the first instruction do not match, and a circuit for indicating a boundary between the first instruction and a next instruction from the stream of instructions based on the boundary marker of the first instruction.

Boundary markers for indicating the boundary of a variable length

An improved cache and organization particularly suitable for superscalar architectures. The cache is organized around trace segments of running programs rather than an organization based on memory addresses. A single access to the cache memory may cross virtual address line boundaries. Branch prediction is integrally incorporated into the cache array permitting the crossing of branch boundaries with a single access.

Dynamic flow instruction cache memory organized around trace segments

A pipeline instruction processor for executing instructions stored in an instruction memory, including a plurality of branch instructions. The instruction processor includes a branch target buffer which contains target instructions and target addresses corresponding to branch instructions. The target instruction data is indexed according to the address of the instruction which precedes the branch instruction. Also included in the branch target buffer is history data indicating whether the branch was taken. The instruction processor also includes two execution units. The present invention employs logic which allows a branch instruction and its target instruction stored in the branch target buffer to be executed concurrently in the two execution units according to the history data stored in the branch target buffer. Since the branch instructions and their target instructions are executed during the same cycle, branch instructions appear to be executed in zero cycles.

Pipeline system for executing predicted branch target instruction in a

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Haifa, Israel

Uri C Weiser