Institute of Microelectronics

Maxim Integrated Products, Inc.

Triquint Semiconductor Corporation

Other

National University of Singapore

Uppili Sridhar

Quanbo Zou

Ranganathan Nagarajan

Pang Dow Foo

Yu Jau Chen

Albert M Bergemont

Joseph P Ellul

Tie Yan

Yubo Miao

Tit Meng Lim

Emmanuel Selvanayagam Zachariah

Rakesh Kumar

Amit Subhash Kelkar

Edward Martin Godshalk

Ralph N Wall

Xuejun Ying

Victor Samper

Hanhua Feng

Shuming Xu

Rick D Lutz

Foo Pang Dow

Masud Hannan

Bai Xu

Zhe Wang

Helmut F Schlaak

Yi-Sheng Anthony Sun

Janak Singh

Carlton Stuebing

Hans Dropmann

Mnoon Yan Loke

Olaf Knueppel

Nazanin Davani

Feng Han Hua

Hui Wing Cheong

Rong Ming Lin

Mong King Lim

Loke Mnoon Yan

Liu Lian Jun

Lo Yong Hong

Maio Yu Bo

Kay Krupka

Elliott Simons

Dirk Wagenaar

Qinxin Zhang

Zhang Qingxin

Yu Bo Miao

Yi Su

A process for producing a magnetic core material is disclosed. The process includes distributing particles within a solution medium to form a colloidal solution. The process further includes modifying a surface chemistry of the particles by adding one or more additives to the colloidal solution. The process further includes gelating the colloidal solution to form the magnetic core material.

Controlling the morphology in metal loaded paste material

A method including: providing a first wafer stack; applying a first bonding layer on the first wafer stack; providing a second wafer stack, where the second wafer stack includes vias; and applying a second bonding layer to the second wafer stack. The vias extend through the second wafer stack and to the second bonding layer. The second bonding layer is bonded to the first bonding layer. A seed layer is applied on a side of the second wafer stack opposite the second bonding layer such that a material of the seed layer (i) contacts the vias, and (ii) extends over and past ends of the second wafer stack and onto the first bonding layer.

Bonded stacked wafers and methods of electroplating bonded stacked wafers

Methods of forming coaxial feedthroughs for 3d integrated circuits that provide excellent isolation of signal paths from the substrate and from adjacent feedthroughs. One method is to form a recess in a substrate and deposit alternate layers of insulation and conductive layers and then thin the substrate to make the layers available from both sides of the substrate, with the first metal layer forming the coaxial conductor and the second metal layer forming the central conductor. Alternatively the coaxial feedthroughs may be formed using a modified pillar process to form the coaxial conductor at the same time as the center conductor is formed so that the coaxial feedthrough is formed without requiring extra steps. Both processes are low temperature processes.

Methods of forming coaxial feedthroughs for 3D integrated circuits

A method of deposition of magnetic nanocomposites. The method comprises providing an electron beam evaporation system having at least two independent hearths with independently controllable electron beams, each to melt and evaporate materials in the respective hearth, each hearth having a respective shutter for selectively controlling the deposition of the respective material in the respective hearth, placing a ferromagnetic material in a first hearth, placing an oxide in a second hearth which, when evaporated and deposited, will form an insulator, maintaining an oxygen environment in the electron beam evaporation system while evaporating the materials in the first hearth and second hearth, and depositing the magnetic nanocomposite on at least one wafer in the electron beam evaporation system. Various aspects of the method are disclosed.

High rate deposition method of magnetic nanocomposites

A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.

A bulk acoustic wave (BAW) resonator is constructed to reduce phase and amplitude ripples in a frequency response. The BAW resonator is fabricated on a substrate 400 &#x3bc;m thick or less, preferably approximately 325 &#x3bc;m, having a first side and a polished second side with a peak-to-peak roughness of approximately 1000 A. A Bragg mirror having alternate layers of a high acoustic impedance material, such as tungsten, and a low acoustic impedance material is fabricated on the first side of the substrate. A BAW resonator is fabricated on the Bragg mirror. A lossy material, such as epoxy, coats the second side of the substrate opposite the first side. The lossy material has an acoustic impedance in the range of 0.01&#xd7; to 1.0&#xd7; the acoustic impedance of the layers of high acoustic impedance material.

Optimal acoustic impedance materials for polished substrate coating to suppress passband ripple in BAW resonators and filters

Methods of forming coaxial feedthroughs forintegrated circuits that provide excellent isolation of signal paths from the substrate and from adjacent feedthroughs. One method is to form a recess in a substrate and deposit alternate layers of insulation and conductive layers and then thin the substrate to make the layers available from both sides of the substrate, with the first metal layer forming the coaxial conductor and the second metal layer forming the central conductor. Alternatively the coaxial feedthroughs may be formed using a modified pillar process to form the coaxial conductor at the same time as the center conductor is formed so that the coaxial feedthrough is formed without requiring extra steps. Both processes are low temperature processes.

A 3D chip package is disclosed that includes a carrier substrate with a first cavity and a second cavity formed therein. A first structure is attached to the carrier substrate at least partially in the first cavity, and a second structure is attached to the carrier substrate at least partially in the second cavity, where the first and second structures include electrical circuitry. A shield layer may be disposed between the carrier substrate and the first structure and/or the second structure for isolating the first structure and/or the second structure at least one of electrically, magnetically, optically, or thermally. In some embodiments, the shield layer may be a dielectric shield layer for dielectrically coupling the first structure and the second structure. The first structure and the second structure may be homogeneous or heterogeneous.

3D chip package with shielded structures

Methods of reducing phase and amplitude ripples in a BAW resonator frequency response by providing a substrate, fabricating a Bragg mirror having alternate layers of a high acoustic material and a low acoustic material on a first surface of the substrate, fabricating a BAW on the Bragg mirror, and coating a second side of the substrate opposite the first side with a lossy material having an acoustic impedance in the range of 0.01&#xd7; to 1.0&#xd7; the acoustic impedance of the layers of high impedance material, the second surface of the substrate being a polished surface. Various embodiments are disclosed.

Bonded wafer packages having first and second wafers bonded together forming a matrix of sealed devices, at least one of the wafers having a plurality of passive devices formed thereon, including at least one BAW resonator within each of the sealed devices, the first wafer having conductor filled through-holes forming electrical connections between the passive devices and connections assessable from outside the sealed devices, the bonded wafers being diced to form individual sealed devices. The devices may be duplexers, interstage filters or other circuits such as VCOs and RF circuits. Various embodiments are disclosed.

Bonded wafer package module

Microrelays and microrelay fabrication and operating methods providing a microrelay actuator positively controllable between a switch closed position and a switch open position. The microrelays are a five terminal device, two terminals forming the switch contacts, one terminal controlling the actuating voltage on an actuator conductive area, one terminal controlling the actuating voltage on a first fixed conductive area, and one terminal controlling the actuating voltage on a second fixed conductive area deflecting the actuator in an opposite direction than the first fixed conductive area. Providing the actuating voltages as zero average voltage square waves and their complement provides maximum actuating forces, and positive retention of the actuator in both actuator positions. Various fabrication techniques are disclosed.

Microrelays and microrelay fabrication and operating methods

Wafer level packaging process for packaging MEMS or other devices. In some embodiments, a MEMS wafer with normal thickness is firstly bonded to a cap wafer of normal thickness, followed by a thinning on the backside of the MEMS wafer. After this, the bonded wafer stack and the capping of the hermetically packaged MEMS devices are still rigid enough to do further processing. On this basis, through vias on the thinned substrate can be easily formed and stopped on the regions to be led out (e.g., metal pads/electrodes, highly doped silicon, etc.). Vias can be partially filled as this is the final surface of process. Even thick metal coated/patterned vias have much more space to relax possible thermal stress, as long as the vias are not completely filled with hard metal(s). Various embodiments are disclosed.

Wafer level packaging process

The invention relates to a method of making an integrated circuit inductor that comprises a silicon substrate and an oxide layer on the silicon substrate. In one aspect, the method comprises depositing an inductive loop on the oxide layer, and making a plurality of apertures in the oxide layer beneath the inductive loop. The method also comprises providing a plurality of bridges adjacent the apertures and provided by portions of the oxide layer between an inner region within the inductive loop and an outer region of the oxide layer without the inductive loop, the inductive loop being supported on the bridges. The method comprises forming a trench in the silicon substrate beneath the bridges, to provide an air gap between the inductive loop and the silicon substrate.

Method of making an integrated circuit inductor wherein a plurality of apertures are formed beneath an inductive loop

Method of fabricating a micro-mirror switching device in single crystal silicon are described. The device is fabricated as three main elements: silicon mirror plate with metal-mirror, secondary actuator, and hinge/spring mechanism to integrate the mirror plate with the actuator. p-n junction is first formed on p-type silicon. Trenches are then etched in n-silicon to define the device element boundaries and filled with silicon dioxide. Three layers of sacrificial oxide and two structural poly-silicon layers are deposited and patterned to form device elements. Novel release processes, consisting of backside electrochemical etching in potassium-hydroxide, reactive ion etching to expose oxide-filled trenches from the bottom, and hydrofluoric acid etching of sacrificial oxide layers and oxide in silicon trenches, form the silicon blocks; those that are not attached to structural poly-silicon are sacrificed and those that are attached are left in place to hold together the switching device elements.

Method of fabricating micro-mirror switching device

Growing community of inventors

Singapore, Singapore

Uppili Sridhar