Globalfoundries U.S. Inc.

Uppili S Raghunathan

Steven M Shank

Vibhor Jain

Yves T Ngu

Megan Elizabeth Lydon-Nuhfer

Sebastian Theodore Ventrone

Qizhi Liu

Alvin Jose Joseph

Rajendran Krishnasamy

Alexander M Derrickson

Johnatan A Kantarovsky

Ramsey M Hazbun

Cameron E Luce

Ajay Raman

Sarah A McTaggart

Jacob M Deangelis

Sarah A Mctaggart

The disclosure provides an isolation stack for a bipolar transistor (BT), and related methods. A structure of the disclosure includes a first isolation layer on a subcollector. A first air gap is between the first isolation layer and a collector of a BT. A second isolation layer is on the first isolation layer and adjacent an intrinsic base of the BT. A third isolation layer is on the second isolation layer, vertically between the second isolation layer and an extrinsic base of the BT. A second air gap is adjacent the third isolation layer and below the extrinsic base.

Isolation stack for a bipolar transistor and related methods

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region; an extrinsic base comprising an emitter opening with an angled sidewall; an emitter within the emitter opening; and an intrinsic base between the emitter and the collector.

Bipolar transistor

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a stepped emitter and methods of manufacture. The structure includes: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.

Bipolar transistor with stepped emitter

Structures with an isolation region and fabrication methods for a structure having an isolation region. The structure includes a semiconductor substrate, a first isolation region surrounding a portion of the semiconductor substrate, a device in the portion of the semiconductor substrate, and a second isolation region surrounding the first isolation region and the portion of the semiconductor substrate.

Isolation regions for charge collection and removal

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Essex Junction, VT, United States of America

Uppili S Raghunathan