Samsung Electronics Co., Ltd.

Ungjin Jang

Sooyong Park

Yongjeong Kim

Seonggwon Jang

A test device configured to test a device under test (DUT) performing an interface of a pulse amplitude modulation (PAM) operation includes a logic generation/determination device configured to generate multiple bits corresponding to a test pattern, first and second drivers configured to generate respective first and second non return to zero (NRZ) signals according to a logic state of respective first and second bits among the multiple bits and output the respective generated first and second NRZ signals via respective first and second channels. The first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit. The first and second high levels are different from each other.

Test devices, test systems, and operating methods of test systems

The test board may include sockets in which a plurality of devices-under-test (DUTs) is inserted, and an auxiliary test device connection tree electrically connected to the sockets. The auxiliary test device connection tree includes at least one first auxiliary test device receiving and outputting a test request from an external apparatus, and at least one second auxiliary test device generating a test clock and a test pattern in response to the test request outputted from the at least one first auxiliary test device, performing a test operation about at least one among the DUTs using the generated test pattern, and outputting whether or not of an error of the test operation to the at least one first auxiliary test device.

Growing community of inventors

Asan-si, South Korea

Ungjin Jang