Texas Instruments Corporation

Uming U Ko

Hugh Thomas Mair

David Barry Scott

Alice Wang

Sumanth Katte Gururajarao

Gordon Gammie

Baher S Haroun

Ramaprasath Vilangudipitchai

Wei Yu Chen

Sami Issa

Anthony Martin Hill

Patrick W Bosshart

Hiep V Tran

Clive D Bittlestone

Bernhard H Andresen

Michael Patrick Clinton

Robert L Pitts

Dharin Nayeshbhai Shah

Franck Benjamin Dahan

Rolf Lagerquist

Girishankar Gurumurthy

Keerthinarayan P Heragu

Wei Dong

Ian Chen

Shannon A Wichman

Stanley C Keeney

Joe F Sexton

Mitra Nasserbakht

Bixia Li

Sudha Thiruvengadam

Kan Lu

Chongjun Jiang

Senthil Kumar Sundaramoorthy

Minh Chau

Pranjal Srivastava

Sumanth K Gururjarao

Glen Roy Balko

Sushma Honnavara-Prasad

Peter H Cumming

Embodiments of the present disclosure provide a power controller, a method of operating a power controller and a semiconductor memory system. In one embodiment, the power controller is for use with a memory and includes an access module configured to provide an active state of the memory to allow memory access. The power controller also includes a retain-till-access module configured to cycle a portion of the memory between the active state and a low leakage data retention state of the memory. The power controller further includes an expanded retain-till-access module configured to extend the active state of the memory for a specified period of time before returning the memory to the low leakage data retention state.

Power controller, a method of operating the power controller and a semiconductor memory system employing the same

An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a 'glitch-free' control for a power switch.

Apparatus, system and method of power state control

Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.

Memory power management systems and methods

A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

System and method for auto-power gating synthesis for active leakage reduction

In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.

Ultra low area overhead retention flip-flop for power-down applications

The present disclosure provides a dual-mode voltage controller, a method of supplying voltage to SRAM periphery circuits and an integrated circuit. In one embodiment, the dual-mode voltage controller is for use with an SRAM array and includes a voltage switching unit connected to a digital core voltage and an SRAM array voltage to form a structure capable of switching at least one SRAM periphery circuit between the digital core voltage and the SRAM array voltage.

Dual mode SRAM architecture for voltage scaling and power management

An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.

Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention scheme

System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as switch arrangement) with a plurality of switches (such as switch) coupling a power supply to the circuitry. Each switch is individually controlled by a control signal and is turned on sequentially. Also coupled to each switch is a pre-driver circuit (such as pre-driver circuit). The pre-driver circuit comprises a potential adjust circuit (such as potential adjust circuit) that rapidly adjusts a voltage potential at the switch and a rate adjust circuit (such as the rate adjust circuit) that accelerates the power ramp-up across the switch once transient currents are no longer a concern. Adjusting the voltage potential so that the switch operates in a saturation mode increases an effective capacitance across the switch and thereby retarding the power ramp-up across the switch.

Potential and rate adjust header switch circuitry reducing transient current

An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.

Performance and area scalable cell architecture technology

An electronic system (). The system comprises circuitry (P) for receiving a system voltage from a voltage supply. The system also comprises circuitry (), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry () for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry () for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability. In selected instances, the circuitry for adjusting adjusts the voltage supplied by the voltage supply to be a voltage greater than the predetermined voltage operating limit while still complying with the predicted lifespan.

Integrated circuit with dynamically controlled voltage supply

A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.

Fast access memory architecture

A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.

Adaptive voltage control and body bias for performance and energy optimization

System and method for detecting transistor failure in large-scale integrated circuits by measuring IDDQ. A preferred embodiment comprises a switch structure for an integrated circuit made up of a plurality of main switches (such as main switch) selectively coupling a power sub-domain to a power source pin, a plurality of pi-switches (such as pi-switch) selectively coupling pairs of power sub-domains, and a plurality of IDDQ switches (such as IDDQ switch) selectively coupling the power sub-domains to a VIDDQ pin. The pi-switches can decouple the power sub-domains while the IDDQ switches can enable the measurement of the quiescent current in the power sub-domains. The use of pi-switches and IDDQ switches can permit the measurement of the quiescent current in the power sub-domains without requiring the use of isolation buffers and needed to powering on and off the integrated circuit between current measurements in the different power sub-domains.

System and method for IDDQ measurement in system on a chip (SOC) design

System and method for reducing voltage fluctuations in an integrated circuit with multiple power domains and sub-domains. A preferred embodiment comprises a plurality of voltage sources and a switching network (such as switching network) wherein outputs from the plurality of voltage sources are inputs. The switching network can couple the outputs of voltage sources (based on a mapping) with the same output voltage levels to reduce voltage fluctuation amongst power domains coupled to the coupled outputs. The coupling may be performed by a switching structure (such as the switching structure) that can controllably electrically couple two outputs.

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Plano, TX, United States of America

Uming U Ko