Motorola Corporation

Umesh Sharma

Howard C Kirsch

Kuo-Tung Chang

Hisao Kawasaki

Michael P Woo

Jim Hayden

Jack Higman

Shih-Wei Sun

John R Yeargain

A nonvolatile memory device includes a floating-gate electrode (14) overlying a surface (24) of a substrate (10). A diffusion barrier layer (34) extends from the substrate surface (24) along a wall surface (30) of the floating-gate electrode (14) to an upper surface (32) of the floating-gate electrode (14) and overlies the upper surface (32). The diffusion barrier layer (34) blocks the silicidation of the floating-gate electrode (14) and prevents ionic contaminants from diffusing to the floating-gate electrode (14). A charge control region (42) of the floating-gate electrode (14) is capacitively coupled to a well region (40) within the substrate (10). The well region (40) functions as a diffused control-gate electrode and regulates the voltage of the floating-gate electrode (14).

Process for fabricating a semiconductor device including a nonvolatile

EPROM cells include T-shaped floating gates (61, 171) and control gates that surround virtually all of the floating gates (61, 171) except for the portion of the floating gates (61, 171) that lie on a gate dielectric layer (51, 151). The EPROM cells may include customized well regions (22, 122) to allow flash erasing or individual cell erasing for electrically erasable EPROMs. Many different configurations of the memory cells are possible. The configurations of the source regions, drain regions, and well regions (22, 122) may be determined by how a user of the memory cells wants to program or erase the memory cells.

Electrically programmable read-only memory cell

A method for fabricating a 1-transistor EEPROM device, which can be programmed and erased by Fowler-Nordheim tunneling includes the formation of a memory gate (28) overlying a tunneling region (22), and aligning source (32) and drain (34) regions in a semiconductor substrate (10), such that a vertically oriented electric field (46) is created in the tunneling region (22). The memory gate (28) is coupled to a contact region (30) by a connecting portion (31). A select gate (14) controls a portion of the channel region in the substrate (10) adjacent to the tunneling region (22). The EEPROM device is programmed by applying a voltage of a first polarity memory gate (28), while applying a voltage of a second polarity to the source region (32), the drain region (34), and to the substrate (10). Under the applied voltages, charge carriers tunnel through a tunnel oxide layer (40) and into a silicon nitride layer (42), located intermediate to the memory gate (28) and the tunnel region (22). To erase the EEPROM device, the polarity of the applied voltages is reversed, and charge carriers of an opposite conductivity type tunnel into the silicon nitride layer (42).

Fabrication process for a 1-transistor EEPROM memory device capable of

Process for forming an electrically programmable read-only memory cell

A nonvolatile SRAM cell (20) includes a six-transistor SRAM cell portion (22) and a three-transistor nonvolatile memory portion (30). The nonvolatile memory portion (30) is connected to one storage node (101) of the SRAM cell portion (22). The nonvolatile SRAM cell (20) is three-dimensionally integrated in four layers of polysilicon. The nonvolatile memory portion (30) includes a thin film memory cell (32) having an oxide-nitride-oxide structure (41), and is programmable with a relatively low programming voltage. The three-dimensional integration of the nonvolatile SRAM cell (20) and relatively low programming voltage results in lower power consumption and smaller cell size.

Method for forming a nonvolatile memory device

An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (2) from the source region (12). The control gate electrode (20) overlies a third channeI region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.

Process of making EEPROM memory device having a sidewall spacer floating

Three-dimensionally integrated nonvolatile SRAM cell and process

An electrically programmable read-only memory cell includes a single crystal silicon pillar having the active region of the memory cell. A memory array of the cells may be configured to act as an EPROM array, an EEPROM array, or a flash EEPROM array. A silicon spacer lies adjacent to each of the silicon pillars and acts as a floating gate for its particular memory cell. A memory cell may have a cell area that is less than one square micron. In an EPROM or a flash EEPROM array, no field isolation is required between the memory cells within the array. Processes for forming the memory cells and the memory array are disclosed.

An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (22) from the source region (12). The control gate electrode (20) overlies a third channel region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.

EEPROM memory device having a sidewall spacer floating gate electrode

The surface area of a polysilicon electrode is increased by sputtering non-coalescing islands (20) of aluminum onto a silicon dioxide layer (18), which is overlying the polysilicon electrode. The sputtering process allows uniform island formation to be achieved independent of the deposition surface. The non-coalescing islands are then used as a mask, and a portion of the buffer layer (22) and a portion of the polysilicon electrode (26) are etched to form pillar-like regions (30) within the polysilicon electrode.

Growing community of inventors

Austin, TX, United States of America

Umesh Sharma