Conexant Systems, Inc.

Newport Fab, LLC

Umesh Sharma

Shyam Krishnamurthy

Hong J Wu

Surya S Bhattacharya

Michael Q Le

Kevin Q Yin

Xiaoming Li

Suryanarayana Shivakumar Bhattacharya

Srinjoy Das

Frank Van Gieson

Qi Mei

An anti-reflective coating for use in the fabrication of a semiconductor device includes a thin oxide layer and an overlying layer of silicon oxynitride. The anti-reflective layer is advantageously used in the fabrication of FLASH memory devices which include a layer of polycrystalline silicon and an underlying layer of silicon nitride. After being used to pattern the polycrystalline silicon and silicon nitride, the anti-reflective coating is removed in a solution of hot phosphoric acid with the removal taking place before the silicon oxynitride is exposed to any elevated temperatures.

Anti-reflective coating and process using an anti-reflective coating

A semiconductor device structure and process for its fabrication includes a first layer of HDP oxide and an overlying layer of silicon oxynitride. Application of the HDP oxide to a pattern of metal structures fills gaps between the metal structures and allows for the void free deposition of the silicon oxynitride layer. The silicon oxynitride layer provides a hard outer coating to the passivation coating and is UV transparent so that, if necessary, non-volatile floating gate memory devices can be UV erased.

Semiconductor device having a passivation layer and method for its fabrication

A method of forming an improved interpoly oxide-nitride-oxide (ONO) stricture in stacked gate memory cells is provided. The top oxide layer of an interpoly ONO stack is formed using Low Pressure Chemical Vapor Deposition (LPCVD) of tetraethylorthosilicate (TEOS). As a result of the relatively low processing temperatures necessary for this step, degradation of the tunnel oxide and memory cell performance associated with high thermal-budget oxide growth processes is greatly reduced. Steam densification of the TEOS layer produces a robust top oxide for the ONO dielectric, and thus, greatly reduces erosion of the top layer TEOS during subsequent processing steps (i.e., in the context of a memory array embedded in CMOS core technology). This step also tends to encourage formation of a very thin silicon oxynitride layer at the interface of the nitride and TEOS layers, thus helping to cure &ldquo;pinholes&rdquo; typically associated the nitride layer and further increasing the quality and reliability of the ONO structure. The improved interpoly ONO structure is found to show lower leakage current for applied electrice fields between 1 to 15 MV/cm as compared to prior art.

Method for fabricating interpoly dielectrics in non-volatile stacked-gate memory structures

Pre-conditioning method and apparatus for mitigating erase-induced stress within flash memory devices are disclosed. The pre-condition method includes subjecting flash memory cell to a short write process to at least partially discharge the cells. The pre-condition process is applied to an entire sector at one time, and is performed immediately prior to erasing (charging) the cells within the sector.

Method and apparatus for pre-conditioning flash memory devices

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Newport Beach, CA, United States of America

Umesh Sharma