Nxp B.v.

Umesh Pratap Singh

Ashish Goel

Ruchi Bora

Ajay Sharma

A validation circuit is placed in vicinity of a critical path for testing the critical path. The validation circuit receives test data from the control circuit for testing the critical path. The test data is indicative of a delay value that is associated with the critical path. The validation circuit generates multiple setup signals and an enable signal to facilitate the testing of the critical path based on the test data. The validation circuit generates a first test signal based on the enable signal, and a second test signal based on the first test signal and the setup signals. The second test signal is a delayed version of the first test signal. The validation circuit compares the first test signal and the second test signal. A mismatch between the first test signal and the second test signal indicates deviation from the delay value.

System and method for validating critical paths of integrated circuits

A memory built in self test (MBIST) controller of an MBIST circuit outputs first data. One or more errors is injected in the first data to produce second data. The second data is stored in the memory block. The memory block outputs the second data stored in the memory block. The MBIST controller receives the second data and detects an error in the second data based on a comparison with the first data, the error indicative of a failure of the MBIST. The MBIST controller provides an indication of failure of the MBIST to a processing core external to the MBIST circuit which performs diagnostic action in response to receiving the indication of failure of the MBIST. The processing core validates implementation of the diagnostic action.

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Hodal, India

Umesh Pratap Singh