University of California

Transphorm Inc.

Cree Gmbh

Japan Science and Technology Agency

Transphorm Technology, Inc.

North Carolina State University

Hughes Aircraft Company

Wolfspeed, Inc.

University of Michigan

Agency of Industrial Science and Technology

Universitaet Bremen

Tansphorm Inc.

Umesh Kumar Mishra

Primit A Parikh

Yifeng Wu

Stacia Keller

Steven P DenBaars

Srabanti Chowdhury

Rakesh K Lal

James Stephen Speck

Arpan Chakraborty

Likun Shen

Ilan Ben-Yaacov

Shuji Nakamura

Robert Coffie

Nicholas A Fichtenbaum

Carl Joseph Neufeld

Yuvaraj Dora

Benjamin A Haskell

Chang Soo Suh

Marcia Moore

Lee McCarthy

Rongming Chu

Rajat Sharma

Troy J Baker

Robert M Farrell

David Michael Rhodes

P Morgan Pattison

Bernd P Keller

James Ibbetson

Scott Thomas Sheppard

Brendan Jude Moran

Alessandro Chini

Michael D Craven

Hugues Marchand

Kwang-Choong Kim

Adam William Saxler

Richard Peter Smith

Daniel Bryce Thompson

James Honea

Robert J Trew

Brian L Swenson

Brian Romanczyk

John Adam Edmond

Toshihide Kikkawa

Lawrence E Larson

Sten Heikman

Charles M Swoboda

Geetak Gupta

Primit Parikh

Tal Margalith

Siddharth Rajan

Akihiko Murai

Ramya Yeluri

Elaheh Ahmadi

Chirag Gupta

Mo Wu

Davide Bisi

Matthew Guidry

Xiang Liu

Xun Zheng

Jeonghee Kim

Christina Ye Chen

Silvia H Chan

Christophe Hurni

Carl C Blake, Jr

Jing Lu

Tomas Apostol Palacios

Debdeep Jena

Wladyslaw Walukiewicz

Loi D Nguyen

Michael J Delaney

Linda M Jelloian

John Kirk Gritters

Matthew A Laurent

David Joseph Kapolnek

Detlef Hommel

Huili Xing

Kamruzzaman Khan

Christian Wurm

Yuuki Enatsu

Yusuke Tsukada

Peter Kozodoy

Mark A Thompson

Haoran Li

Bernd Peter Keller

Anchal Agarwal

Tomas A Palacios Gutierrez

Man-Hoi Wong

Yi Pei

Man Hoi Wong

Carsten Kruse

Stephan Figge

Chuck Swoboda

Prashant Chavarkar

Ioulia P Smorchkova

Rakesh Lai

Steven Wienecke

Steven Denbaars

A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.

Lateral III-nitride devices including a vertical gate module

The disclosure describes the use of strain to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition

III-N based material structures, methods, devices and circuit modules based on strain management

A substrate comprising a III-N base layer comprising a first portion and a second portion, the first portion of the III-N base layer having a first natural lattice constant and a first dislocation density; and a first III-N layer having a second natural lattice constant and a second dislocation density on the III-N base layer, the first III-N layer having a thickness greater than 10 nm. An indium fractional composition of the first III-N layer is greater than 0.1; the second natural lattice constant is at least 1% greater than the first natural lattice constant; a strain-induced lattice constant of the first III-N layer is greater than 1.0055 times the first natural lattice constant; and the second dislocation density is less than 1.5 times the first dislocation density.

Method to control the relaxation of thick films on lattice-mismatched substrates

An electronic device including a substrate a group III-V layer on or above the substrate, wherein the III-V layer has an in-plane lattice constant that is greater than that of gallium nitride or wherein the III-V layer is at least partially relaxed; and an active region including a coherently strained group III-V channel layer on or above the III-V layer; wherein electron mobility in the channel layer is increased by the strain. Structures with an in-plane lattice constant that is smaller than that of gallium nitride are used for increasing the hole mobility by strain.

High mobility group-III nitride transistors with strained channels

Described herein are lateral III-N (e.g., GaN) devices having a III-N depleting layer. A circuit includes a depletion-mode transistor with a source connected to a drain of an enhancement-mode transistor. The gate of the depletion-mode transistor and the gate of the enhancement-mode transistor are biased at zero volts, and the drain of the depletion-mode transistor is biased at positive voltage to block a current in a forward direction. Then, the bias of the gate of the enhancement-mode transistor is changed to a first voltage greater than the threshold voltage of the enhancement-mode transistor and a first current is allowed to flow through the channel in a forward direction. Then, the bias of the gate of the depletion-mode transistor is changed to a second voltage and a second current is allowed to flow through the channel in a forward direction where the second current is greater than the first current.

N-polar devices including a depleting layer with improved conductivity

A transistor comprising an active region having a channel layer, with source and drain electrodes formed in contact with the active region and a gate formed between the source and drain electrodes and in contact with the active region. A spacer layer is on at least part of the surface of the plurality of active region between the gate and the drain electrode and between the gate and the source electrode. A field plate is on the spacer layer and extends on the spacer and over the active region toward the drain electrode. The field plate also extends on the spacer layer over the active region and toward the source electrode. At least one conductive path electrically connects the field plate to the source electrode or the gate.

Wide bandgap transistors with gate-source field plates

A field effect transistor comprising a buffer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the device.

Wide bandgap field effect transistors with source connected field plates

Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.

III-N transistor structures with stepped cap layers

An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.

Method to achieve active p-type layer/layers in III-nitrtde epitaxial or device structures having buried p-type layers

A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous AlSiO layer with 0.2&#x3c;x&#x3c;0.8; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.

Enhancement mode III-nitride devices having an Al-SiO gate insulator

A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.

III-nitride devices including a graded depleting layer

A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As illustrated herein, a thin InGaN layer introduced in the channel increases the carrier density, reduces the electric field in the channel, and increases the carrier mobility. The dependence of p on InGaN thickness (InGaN) and indium composition (In) was investigated for different channel thicknesses. With optimizedInGaN andIn, significant improvements in electron mobility were observed. For a 6 nm channel HEMT, the electron mobility increased from 606 to 1141 cm/(V&#xb7;s) when the 6 nm thick pure GaN channel was replaced by the 4 nm GaN/2 nm InGaN composite channel.

Structure for increasing mobility in a high electron mobility transistor

A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

Technique for the growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices

Growing community of inventors

Santa Barbara, CA, United States of America

Umesh Kumar Mishra