Dell Products Inc.

Dell Poducts L.p.

Umesh Chandra

Bhyrav M Mutnury

Chun-Lin Liao

Mallikarjun Vasa

Timothy Thinh Mai

Hamza S Rahman

Arun Reddy Chada

Douglas E Wallace

Han Deng

Henry M Wolst

A printed circuit board (PCB), including: a processing unit; a plurality of layers; and a plurality of vias, each via extending through two or more of the layers, wherein a first via of the plurality of vias has a first pad at a first layer of the plurality of layers and a second via of the plurality of vias has a second pad at the first layer of the plurality of layers, wherein the first pad is conjoined with the second pad to form a first heatsink at the first layer that dissipates heat away from the processing unit.

Printed circuit board (PCB) including heatsinks

A high-speed transmission circuit comprises, as part of a signal path, a connector pin disposed on a pad that comprises an unused pad region. The unused pad region is not considered part of the signal path but is part of a resonant sub-circuit. In various embodiments, by properly adjusting the dimensions of the pad region and other structures in the high-speed transmission circuit, resonant frequencies of the sub-circuit are shifted to a frequency range that is outside of the frequency range of interest in the signal path, thereby, reducing insertion loss and increasing signal integrity without compromising mechanical stability.

Surface mount pads for next generation speeds

In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may measure at least one of a first height value and a first width value of a first eye diagram of a first signal; measure at least one of a second height value and a second width value of a second eye diagram of a second signal; determine at least one of a height difference value and a width difference value respectively between the at least one of the first height value and the first width value of the first eye diagram and the at least one of the second height value and the second width value of the second eye diagram; and determine that the at least one of the height difference value and the width difference value respectively meets or exceeds a height threshold value or a width threshold value.

System and method of determining humidity levels within information handling systems

A zoned dielectric loss circuit board system includes a board. A first differential trace is included in the board. A dielectric layer is included the board and that includes a first dielectric layer zone that engages the first differential trace and that includes first dielectric loss characteristics, and a second dielectric layer zone that is located immediately adjacent the first dielectric layer zone and that includes second dielectric loss characteristics that are greater than the first dielectric loss characteristics. A second differential trace may be included in the board in engagement with the second dielectric layer zone, and may have a second trace length that is shorter than a first trace length of the first differential trace.

Zoned dielectric loss circuit board system

A high-speed signal subsystem testing system includes a processing system having a transmitter and a receiver, a loop back subsystem coupled to the transmitter and receiver to provide a testing communication path between the transmitter and the receiver, and a communication path testing engine coupled to the transmitter and the receiver. The communication path testing engine generates test signal(s) and transmits the test signal(s) via the transmitter and through the testing communication path provided by the loop back subsystem and, in response, receives test signal result(s) via the receiver and through the testing communication path provided by the loop back subsystem, The communication path testing engine processes the test signal result(s) to generate a testing impedance profile for the testing communication path, and compares the testing impedance profile to an expected impedance profile to determine whether a testing communication path issue exists in the testing communication path.

High-speed signal subsystem testing system

A high-speed signal subsystem testing system tests a processor transmitter and receiver coupled to a connector via a transmitter trace and a receiver trace, respectively. A transmitter test circuit on a testing board coupled to the connector compares a transmitter voltage received from the transmitter via the transmitter trace and the connector to a common mode voltage range and, in response to the transmitter voltage being outside the common mode voltage range, provides a transmitter trace issue signal. A receiver test circuit on the testing board coupled to the connector transmits a first test voltage towards the receiver, compares a second test voltage detected at the receiver test circuit in response to transmitting the first test voltage towards the receiver to a reference test voltage and, in response to the second test voltage being above the reference test voltage, provides a receiver trace issue signal.

A high-speed transmission circuit design reduces or eliminates the presence of unwanted stub-effects and avoids uncontrolled line impedances that in existing circuits cause impedance mismatches that give rise to unwanted reflections and, ultimately, degrade signal integrity, e.g., in belly-to-belly configurations involving Quad Small Form-Factor Pluggable Double Density (QSFP DD) connectors. In various embodiments, by preventing overcrowding of signal lines, the circuit design further reduces crosstalk and increases signal integrity.

High-speed trace breakout methods and systems

A high-speed transmission circuit comprises a connector pin that serves as part of a signal path, has a first conductivity, and has a connector pin leg that is coupled to a pad that has a second conductivity lower than the first conductivity. The connector pin leg and at least a portion of the pad form a resonant sub-circuit coupled to the signal path. The second conductivity causes a reduction in insertion loss in the signal path by damping a current in the resonant sub-circuit.

Plated pads and leads for surface mount technology connections

A multi-layer PCB has conductive vias () passing through multiple layers. A layer may have a conductive non-functional feature () physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad ().

Printed circuit boards with non-functional features

A corrosion monitoring/alerting system includes a chassis. A corrosion monitoring subsystem identifies a current humidity and a current temperature in the chassis, determines that the current humidity is above a corrosion-alert humidity and the current temperature is below a corrosion-alert temperature and, in response, generates a first corrosion alert signal. A corrosion alert subsystem identifies the first corrosion alert signal and, in response, transmits a first recommended corrosion remediation action communication. The corrosion monitoring subsystem may also transmit a test current through a test computing subsystem connection, determine that a test voltage generated in response to transmitting the test current through the test computing subsystem connection is below a corrosion-alert voltage and, response, generate a second corrosion alert signal. The corrosion alert subsystem may identify the second corrosion alert signal and, in response, transmit a second recommended corrosion remediation action communication.

Corrosion monitoring/alert system

A differential trace pair system includes a board including a board structure having a first, a second, a third, and a fourth board structure member, wherein a distance between the first and the third board structure members is longer than a distance between the second and the fourth board structure members. The differential trace pair system further includes a differential trace pair that includes a first differential trace extending between the first and the third board structure members and a second differential trace extending between the second and the fourth board structure members. The second differential trace having a serpentine structure that includes a first portion that continuously transitions away from the first differential trace and a second portion that is contiguous with the first portion, the second portion continuously transitions towards the first differential trace.

Information handling system comprising a processor coupled to a board and including a differential trace pair having a first straight differential trace and a second serpentine shape differential trace

A differential trace pair system includes a board having a first, a second, a third, and a fourth board structure member. A differential trace pair in the board includes a first differential trace extending between the first and the third board structure members, and a second differential trace extending between the second and the fourth board structure members. The differential trace pair includes a serpentine region that includes a first portion and a second portion where the first and the second differential traces have a first width, are substantially parallel, and spaced apart by a first differential trace pair spacing, and a third portion in which the second differential trace includes a second width that is greater than the first width, the first and second differential traces are substantially parallel and spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.

Differential trace pair system

A circuit board pad connector system includes a connector that is configured to mount to a connector pad that is included on a circuit board. The connector includes a connector lead frame. A lead portion is provided on the connector lead frame such that the lead portion is oriented substantially perpendicularly relative to the connector pad when the connector is mounted to the connector pad. A first mounting portion is provided on the connector lead frame, is configured to mount the connector to the connector pad, and extends in a first direction that is substantially perpendicular relative to the lead portion. A second mounting portion is provided on the connector lead frame, is configured to mount the connector to the connector pad, and extends in a second direction that is different than the first direction and that is substantially perpendicular relative to the lead portion.

Growing community of inventors

Santa Cruz, CA, United States of America

Umesh Chandra