Fujitsu Corporation

Umeo Oshio

Yoshifumi Mizoshita

Keiji Aruga

Takao Sugawara

Takenori Ohshima

Yoshiyuki Nagasaka

A DC-DC converter includes N capacitors having identical capacitances, initially coupled in series, and supplied with an external power supply voltage to be charged thereby, and an circuit for coupling the N capacitors in parallel and varying a duty ratio of a charging timing, so as to vary an internal power supply voltage which is output from the DC-DC converter.

DC-DC converter and storage apparatus

A phase-synchronizing circuit includes a phase error detection circuit detecting a phase-error in a given clock signal and producing an output indicative of the phase-error as a first phase-error signal, a phase-error creating circuit creating a second phase-error signal determined so as to minimize a time for establishing a phase-synchronization for the clock signal, and a selection circuit selectively supplying the first or second phase-error signal selectively to a phase control circuit.

Phase-synchronization method and circuit for establishing a phase-synchronization for signals with reduced time

A detection circuit in a magnetic recording and playback apparatus which uses partial response and the maximum likelihood method, in which neither the size of the detection circuit nor the power consumption increase when the partial response order n increases. In this detection circuit, in the circuit that detects a signal read out from a head, either a plurality of equalizers for different target equalization waveforms, or a single variable target equalizer is provided. A detector for the waveform output from an equalizer is connected in series with the detector. A plurality of combinations, each formed by an equalizer and a detector, is connected in parallel to the output of a filter, the outputs of the combinations of equalizers and detectors being input to a switching circuit, which is controlled by a switching control means. The switching control means controls the switching circuit so that just one of the combinations of equalizer and detectors is selected as the detector output. If a variable target equalizer, which is capable of generating two or more different types of equalization waveforms, is used as the equalizer, it is possible to reduce the number of equalizers to one.

Detecting circuit for read signal from magnetic recording system using partial response

Two LSIs are driven with different power supply voltages. An interface circuit which outputs a constant current corresponding to a logic signal to a first LSI and stopping the output of the constant current is provided in the first LSI. An interface circuit which generates a logic signal having a level conforming to the second LSI, based on the constant current, is provided in the second LSI.

Interface circuit and signal transmission method

A finite impulse response circuit includes a delay line having a plurality of taps, receiving an input signal, a multiplying part for multiplying coefficients to signals obtained from the taps and adding multiplied results, and a shaping part for shaping the input signal by adjusting the coefficients. The shaping part includes a first tap coefficient setting circuit for correcting a signal distortion which is asymmetrical to right and left with respect to a signal point, and a second tap coefficient setting circuit for correcting a signal distortion which is symmetrical to the right and left with respect to the signal point. The first tap coefficient setting circuit sets the coefficient independently of the second tap coefficient setting circuit.

Finite impulse response circuit and disk unit

A training pattern which is used for a waveform equalization is preliminarily recorded on a disk medium and the waveform equalization to suppress an interference between bits of a read waveform by an adaptive type equalizer is performed. An error detector executes a training operation for adjusting an equalization amount of the adaptive type equalizer so as to minimize an error due to the interference between bits of the read waveform on the basis of the training pattern read out from the disk medium. A bit pattern detector detects a predetermined bit pattern '00' included in the training pattern and instructs the start of the training operation to the error detector by the detection of the first bit pattern '00'. A counter counts the number of detection times of the bit pattern '00' by the bit pattern detector and instructs the end of the training operation to the error detector when the number of detection times reaches a predetermined value.

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Kawasaki, Japan

Umeo Oshio