Micron Technology Incorporated

Intel Corporation

Umberto Siciliani

Tommaso Vali

Violante Moschiano

Walter Di Francesco

Andrea Giovanni Xotta

Anna Chiara Siviero

Michele Incarnati

Mattia Cichocki

Maria-Luisa Gallese

Andrea Smaniotto

Dheeraj Srinivasan

Ali Mohammadzadeh

Floriano Montemurro

Luca De Santis

Michele Piccardi

Terry M Grunzke

Giuseppe D'Eliseo

Daniel J Hubbard

Agostino Macerola

Anna Scalesse

Luca DeSantis

Guido Luciano Rizzo

Kishore Kumar Muchherla

Aaron S Yip

James Fitzpatrick

Giovanni Santin

Huai-Yuan Tseng

Jung Sheng Hoei

Eric N Lee

Giulio Giuseppe Marotta

Ting Luo

June Lee

Karl David Schuh

Akira Goda

Jeffrey S McNeil, Jr

Luigi Pilolli

Antonino Pollio

Tao Liu

Dionisio Minopoli

Giuseppe Ferrari

Carminantonio Manganelli

Luigi Esposito

Domenico Monteleone

Dave Scott Ebsen

Walter Di-Francesco

Giovanni Maria Paolucci

Gianfranco Valeri

Rohitkumar Makhija

Federica Paolini

Allison Jayne Olson

Enrico Favaro

Leo Raimondo

Davide Esposito

Violante Moshciano

Control logic in a memory device initiates a programming operation to program a set of memory cells of the memory device to a target programming level of a set of programming levels. During execution of the programming operation, a programming status associated with the set of memory cells. In response to determining the programming status satisfies a condition, causing a release of a set of data associated with the programming operation from a cache register.

Programming operation using cache register release in a memory sub-system

A memory device includes a page buffer with multiple registers and a memory array, configured as single-level cell (SLC) memory, including a set of sub-blocks coupled with the page buffer. Control logic is operatively coupled with the page buffer and causes a first page of SLC data to be stored in the multiple registers. The control logic causes a subsequent page of the SLC data to be stored in the multiple registers. The control logic causes the subsequent page and the first page of the SLC data stored in the multiple registers to be concurrently programmed to the set of sub-blocks. The control logic causes at least some of the operations for programming the first page and the subsequent page to the set of sub-blocks to be performed in parallel.

Hybrid parallel programming of single-level cell memory

Control logic in a memory device receives, from a requestor, a request to read data from the memory array, the request comprising an indication of a segment of the memory array where the data is stored and performs, using previously configured read operation parameters, a first read operation to read the data and a write temperature associated with the data from the memory array. The control logic determines whether the previously configured read operation parameters satisfy a temperature criterion and responsive to determining that the previously configured read operation parameters do not satisfy the temperature criterion, configures the memory device with updated read operation parameters, and performs, using the updated read operation parameters, a second read operation to read the data from the memory array.

Cross-temperature compensation in a memory sub-system

Apparatuses, systems, and methods for algorithm qualifier commands are described according to embodiments of the present disclosure. One example method can include executing an algorithm qualifier command on a memory device and performing an operation on the memory device for a command sequence that follows the algorithm qualifier command using a number of settings indicated by the algorithm qualifier command. The algorithm qualifier command can indicate a number of settings to use while performing the operation on the memory device.

Algorithm qualifier commands

Memories might include a controller configured to cause the memory to prepare a first plurality of memory cells of a block of memory cells for programming from an initialization state of the block of memory cells, program the first data to the first plurality of memory cells, and, in response to receiving a write command associated with a second address corresponding to the block of memory cells and with second data before successfully verifying programming of the first data to the first plurality of memory cells, prepare a second plurality of memory cells of the block of memory cells corresponding to the second address for programming without returning the block of memory cells to the initialization state after programming the first data to the first plurality of memory cells.

Memories for performing successive programming operations

A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled to the array of memory cells. The control logic performs operations including: causing hardware initialization of a set of sub-blocks that are to be programmed within the array of memory cells; causing a first sub-block of the set of sub-blocks to be preconditioned for a program operation; causing multiple pages of data to be programmed to respective ones of the set of sub-blocks; and selectively causing a program verify to be performed on memory cells of the set of sub-blocks after programming the multiple pages of data.

Shortened single-level cell memory programming

A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

Independent plane architecture in a memory device

Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.

Memory devices for suspend and resume operations

Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.

Setting switching for single-level cells

Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.

Two-pass corrective programming for memory cells that store multiple bits and power loss management for two-pass corrective programming

A memory device includes a page buffer with a cache register and data registers, a memory array with a set of sub-blocks of memory cells configured as single-level cell (SLC) memory, and control logic. The control logic performs operations including: causing a first page of SLC data to be stored in the cache register; causing the first page of the SLC data to be moved from the cache register to a first data register; causing a subsequent page of the SLC data to be stored in the cache register; causing the SLC data stored in the cache register and in the data registers to be concurrently programmed to the set of sub-blocks, where the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block; and causing a subset of the operations for programming the set of sub-blocks to be performed in parallel.

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a first read operation on the memory device to retrieve first data; determining, from the first data, second data indicative of a write temperature associated with the first data, wherein the write temperature is indicative of a temperature measured during a write operation; determining a read voltage value based on the second data; and performing a second read operation on the memory device using the read voltage value to obtain the first data.

Cross-temperature compensation in non-volatile memory devices

Control logic in a memory device initiates an express programming operation to program the set of memory cells to a target programming level of a set of programming levels. A set of data associated with the express programming operation is stored in a cache register. At a first time during the execution of the express programming operation, a prediction operation is executed to determine a prediction result corresponding to a programming status of the set of memory cells. The prediction result is compared to a threshold level to determine whether a condition is satisfied. The release of the set of data from the cache register is caused in response to satisfying the condition.

Express programming using advanced cache register release in a memory sub-system

Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform a program operation and in response to the command to perform the program operation, begin execution of the program operation. The controller might be further configured to while executing the program operation, receive a command to perform a read operation; in response to the command to perform the read operation, suspend the execution of the program operation; and with the execution of the program operation suspended, execute the read operation.

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Rubano, Italy

Umberto Siciliani