International Business Machines Corporation

Umberto Garofano

Ivan L Wemple

Charles S Chiu

James E Jasmin

Igor Arsovski

Jeanne P Bickford

Nazmul Habib

Tad Jeffrey Wilder

Eric W Tremble

Kurt A Carlsen

Bruce Balch

Ze Gui Pang

David Toub

A method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models. The method includes collecting power supply noise monitor data from an integrated circuit having one or more power supply noise monitors connected between a power supply and respective scan cells of a scan chain and one or more functional circuits connected to the scan chain by scanning a power supply noise generation pattern into the scan chain and scanning a resultant pattern out of the scan chain; converting the resultant data into actual values of selected power supply parameters; generating simulated values of the selected power supply parameters using a power supply noise simulation model based on design data of the integrated chip; comparing the actual values of the selected power supply parameters to the simulated values of the selected power supply parameters; and modifying the power supply noise simulation model based on the comparing.

Method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models

Methods, systems, computer programs, etc., determine the required number of decoupling capacitors, and approximate locations for the decoupling capacitors, for a region of an integrated circuit. Switching elements of the region are entered into a simulation program running on a computerized device. Also, a power distribution model of the region is entered into the simulation program, and a power-supply voltage compression target is entered into the simulation program. These methods, systems, etc., generate an upper number of decoupling capacitors required to satisfy the compression target when all the switching elements concurrently switch. For each switching element, the methods, systems, etc., generate a specific number of decoupling capacitors required to satisfy the compression when only the element switches, calculate a fraction of the specific number to the upper number, assign the fraction of the total number of decoupling capacitors to each switching circuit element, and place the fraction of the total number of decoupling capacitors in electrical proximity to the element.

Early decoupling capacitor optimization method for hierarchical circuit design

A method of integrated circuit design and, more particularly, a method and system to optimize semiconductor products for power, performance, noise, die area, and cost through use of variable power supply voltage compression. The method is implemented in a computer-based tool and includes: embedding relationships in an optimization tool running on a computing device, wherein the relationships are based at least partly on performance, power-supply noise, die area, and power; inputting a set of product data and a set of technology data in the optimization tool running on the computing device; and determining product design parameters including power supply voltage, switching-noise-induced power supply voltage variation, and decap area. The determining is based on the relationships, the product data, and the technology data and is performed using the computing device running the optimization tool.

Method and system to optimize semiconductor products for power, performance, noise, and cost through use of variable power supply voltage compression

A method, system and program product for creating a simplified equivalent model for an IC that can be used for detailed analysis. The equivalent model takes into consideration the effects of all the I/O placement regardless of the non-uniformity of I/O placement. The equivalent model is generated, in part, by partitioning the IC into simulation windows and converting I/Os within each simulation window to a current source having the same current change rate, and then running a simulation on this intermediate model. A current change rate observed for a simulation window is then used to convert back to actual I/Os to create the equivalent model. The equivalent model can be simulated using conventional software, e.g., SPICE, for more detailed analysis such as signal integrity, timing of I/Os and noise.

Integrated circuit and package modeling

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Essex Junction, VT, United States of America

Umberto Garofano