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Umamaheswara Vemulapati

Munaf Rahimo

Martin Arnold

Jan Vobecky

Marco Bellini

Friedhelm Bauer

Florin Udrea

Lars Knoll

Iulian Nistor

Jürgen Schuderer

Renato Minamisawa

Ulrich Schlapbach

Neophythos Lophitis

Lulian Nistor

Christian Spindler

A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.

Power semiconductor module

A bidirectional thyristor device includes a semiconductor wafer with a number of layers forming pn junctions. A first main electrode and a first gate electrode are arranged on a first main side of the wafer. A second main electrode and a second gate electrode are arranged on a second main side of the wafer. First emitter shorts penetrate through a first semiconductor layer and second emitter shorts penetrate through a fifth semiconductor layer. In an orthogonal projection onto a plane parallel to the first main side, a first area occupied by the first semiconductor layer and the first emitter shorts overlaps in an overlapping area with a second area occupied by the fifth semiconductor layer and the second emitter shorts. The overlapping area, in which the first area overlaps with the second area, encompasses at least 50% of a total wafer area occupied by the semiconductor wafer.

Bidirectional phase controlled thyristor (BiPCT)&#x2014;a new semiconductor device concept

A semiconductor module comprises reverse conducting IGBT connected in parallel with a wide bandgap MOSFET, wherein each of the reverse conducting IGBT and the wide bandgap MOSFET comprises an internal anti-parallel diode. A method for operating a semiconductor module with the method including the steps of: determining a reverse conduction start time, in which the semiconductor module starts to conduct a current in a reverse direction, which reverse direction is a conducting direction of the internal anti-parallel diodes; applying a positive gate signal to the wide bandgap MOSFET after the reverse conduction start time; determining a reverse conduction end time based on the reverse conduction start time, in which the semiconductor module ends to conduct a current in the reverse direction; and applying a reduced gate signal to the wide bandgap MOSFET a blanking time interval before the reverse conduction end time, the reduced gate signal being adapted for switching the wide bandgap MOSFET into a blocking state.

Switching of paralleled reverse conducting IGBT and wide bandgap switch

A power semiconductor device includes a semiconductor wafer having a first main side surface and a second main side surface. The semiconductor wafer includes a first semiconductor layer having a first conductivity type and a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface. The first semiconductor regions have a second conductivity type, which is different from the first conductivity type. Therein, the first semiconductor is a layer of hexagonal silicon carbide. The first semiconductor regions are regions of 3C polytype silicon carbide.

Silicon carbide superjunction power semiconductor device and method for manufacturing the same

A high power semiconductor device with a floating field ring termination includes a wafer, wherein a plurality of floating field rings is formed in an edge termination region adjacent to a first main side surface of the wafer. At least in the termination region a drift layer, in which the floating field rings are formed, includes a surface layer and a bulk layer wherein the surface layer is formed adjacent to the first main side surface to separate the bulk layer from the first main side surface and has an average doping concentration which is less than 50% of the minimum doping concentration of the bulk layer. The drift layer includes a plurality of enhanced doping regions, wherein each one of the enhanced doping regions is in direct contact with a corresponding one of the floating field rings at least on a lateral side of this floating field ring, which faces towards the active region. The relatively low doped surface layer and the enhanced doping regions increase the electric field coupling from floating field ring to floating field ring, thus allowing an area efficient termination structure. Each enhanced doping region extends to at least the same depth as the one of the corresponding floating field ring.

Area efficient floating field ring termination

In a power semiconductor device of the application a total number n of floating field rings (_to_) formed in a termination area is at least 10. For any integer i in a range from i=2 to i=n, a ring-to-ring separation dbetween an i-th floating field ring and a directly adjacent (i&#x2212;1)-th floating field ring, when counting the floating field rings (_to_) along a straight line starting from a main pn-junction and extending in a lateral direction away from the main pn-junction, is given by the following formula: d=d+&#x3a3;&#x394;for i=2 to n, wherein dis a distance between the innermost floating field ring (10_1) closest to the main pn-junction and the main pn-junction, and wherein: &#x394;&#x2212;0.05&#xb7;&#x394;&#x3c;&#x394;&#x3c;&#x394;+0.05&#xb7;&#x394;for j=1 to I&#x2212;2, 2&#xb7;&#x394;&#x3c;|&#x394;|&#x3c;10&#xb7;&#x394;. for j=I&#x2212;1, 0.95&#xb7;&#x394;&#x3c;&#x394;&#x3c;1.05&#xb7;&#x394;for j=I to n&#x2212;1, &#x394;&#x3e;0.1 &#x3bc;m, and &#x2212;&#x394;/2&#x3c;&#x394;&#x3c;&#x394;/2, wherein I is an integer, for which 3&#x2264;l&#x2264;n/2.

Power semiconductor device with floating field ring termination

The invention relates to a turn-off power semiconductor device comprising a plurality of thyristor cells, each thyristor cell comprising a cathode region; a base layer; a drift layer; an anode layer; a gate electrode which is arranged lateral to the cathode region in contact with the base layer; a cathode electrode; and an anode electrode. Interfaces between the cathode regions and the cathode electrodes as well as interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar. In addition, the base layer includes a gate well region extending from its contact with the gate electrode to a depth, which is at least half of the depth of the cathode region, wherein, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region and the gate well region at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 &#x3bc;m from the cathode region. The base layer includes a compensated region of the second conductivity type, the compensated region being arranged directly adjacent to the first main side and between the cathode region and the gate well region, wherein the density of first conductivity type impurities relative to the net doping concentration in the compensated region is at least 0.4.

Flat gate commutated thyristor

A bidirectional power semiconductor device with full turn-off control in both current directions and improved electrical and thermal properties is provided, the device comprises a plurality of first gate commutated thyristor (GCT) cells and a plurality of second GCT cells alternating with each other, a first base layer of each first GCT cell is separated from a neighbouring second anode layer of a neighbouring second GCT cell by a first separation region, and a second base layer of each second GCT cell is separated from a neighbouring first anode layer of a neighbouring first GCT cell by a second separation region.

Bidirectional power semiconductor

A RC power semiconductor is provided which comprises a plurality of diode cells and a plurality of GCT cells. Each GCT cell comprises a first cathode layer with at least three cathode layer regions, which are separated from each other by a base layer. In orthogonal projection onto a plane parallel to the first main side each one of the cathode layer regions is strip-shaped and a width (w, w'), wherein the diode cells alternate with the GCT cells in a lateral direction in at least a mixed part, wherein in each GCT cell, the width (w&#x2032;) of each one of the two outer cathode layer regions next to a diode cell neighboring to that GCT cell is less than the width (w) of any intermediate cathode layer region between the two outer cathode layer regions in that GCT cell.

Reverse conducting power semiconductor device

A reverse-conducting power semiconductor device with a wafer has first and second main sides which are arranged opposite and parallel to each other. The device includes a plurality of diode cells and a plurality of gate commutated thyristors (GCT) cells. Each GCT cell includes layers of a first conductivity type (e.g., n-type) and a second conductivity type (e.g., p-type) between the first and second main sides. The device includes at least one mixed part in which diode anode layers of the diode cells alternate with first cathode layers of the GCT cells. In each diode cell, a diode buffer layer of the first conductivity type is arranged between the diode anode layer and a drift layer such that the diode buffer layer covers lateral sides of the diode anode layer from the first main side to a depth of approximately 90% of the thickness of the diode anode layer.

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Wettingen, Switzerland

Umamaheswara Vemulapati