Intel Corporation

Hewlett-packard Development Company, L.p.

Hewlett-packard Development, L.p.

Uma Srinivasan

Konrad K Lai

Ravi Rajwar

Mingqiu Sun

Suresh Srinivas

Stephen H Dohrmann

Simon C Steely, Jr

Dale Calvin Morris

Kent D Glossop

Kermin Elliott Fleming, Jr

Dz-Ching Ju

Carol Linda Thompson

Yongzhi Zhang

Richard Eugene Hank

Jim Sukha

Kevin Nomura

Methods, apparatus, systems and articles of manufacture to compiler compile code to generate dataflow code are described. An example compiler apparatus includes an intermediate representation transformer to transform input software code to intermediate representation code; an instruction selector to insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code; and a target machine transformer to: convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code; and allocate registers within the dataflow intermediate representation code.

Methods and apparatus to compile code to generate data flow code

Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes intercepting a processor request to apply the lock on the object, identifying a performance history of the object based on a number of instances of contention, reducing computing resources of the processor by, when the number of instances is below a threshold value, generating a lock bypass for the object to cause speculative execution of target code within the object, and preventing speculative execution by applying the lock on the object when the number of instances is above the threshold value.

Methods and apparatus to manage speculative execution of object locks by diverting the speculative execution of target code

Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes receiving an object lock request from a processor, the lock request associated with object lock code to lock an object, and generating object lock-bypass code based on a type of the processor, the object lock-bypass code to execute in a managed runtime in response to receiving the object lock request. The example method also includes identifying a type of instruction set architecture (ISA) associated with the processor, invoking a checkpoint instruction for the processor based on the identified ISA, suspending the object lock code from executing and executing target code when the object is uncontended, and allowing the object lock code to execute when the object is contended.

Method and apparatus to bypass object lock by speculative execution of generated bypass code shell based on bypass failure threshold in managed runtime environment

A method of efficient code generation for modulo scheduled uncounted loops includes: assigning a given stage predicate to each instruction in each stage, including assigning a given stage predicate to each instruction in each speculative stage; and using the stage predicate to conditionally enable or disable the execution of an instruction during the prologue and epilogue execution.

Method and apparatus for efficient code generation for modulo scheduled uncounted loops

Optimizing compiler performance by applying data speculation within modulo scheduled loops to achieve a higher degree of instruction-level parallelism. The compiler locates a schedule for specifying an order of execution of the instructions and allocates rotating registers for the instruction execution. Based upon the schedule and the register allocation, the compiler determines an initiation interval specifying a number of instruction issue cycles between initiation of successive iterations related to the scheduling of the instructions.

Data speculation within modulo scheduled loops

In a computer having rotating registers, a schedule-assigner for allocating the rotating registers. The scheduler-assigner includes a software-pipelined instruction scheduler that generates a first software-pipelined instruction schedule based on an intermediate representation that has data flow information in SSA form. The scheduler-assigner also includes a rotating register allocator that designates live ranges of loop-variant variables in the first software-pipelined instruction schedule as being allocated to rotating registers, when available. The first software-pipelined instruction schedule may be a modulo schedule. When a rotating register is not available, the software-pipelined instruction scheduler may generate a second software-pipelined instruction schedule having an initiation interval greater than the initiation interval of the first software-pipelined instruction schedule.

Method, apparatus, and product for optimizing compiler with rotating register assignment to modulo scheduled code in SSA form

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Sunnyvale, CA, United States of America

Uma Srinivasan