International Business Machines Corporation

Uma Srinivasan

William Vincent Huott

Chandrasekharan Kothandaraman

Yuen H Chan

Adam J McPadden

Thomas J Knips

Stephen Wu

Matthew Steven Hyde

Antonio R Pelella

Gregory J Fredeman

Daniel Rodko

Arthur D Tuminaro

Ryan T Freese

Jatinder K Wadhwa

Kirk David Peterson

K Paul Muller

Kevin W Kark

Akil Khamisi Sutton

John B DeForge

Thomas E Miller

Egduard Ramon Jauregui

Timothy Meehan

Hyong Uk Kim

Pamela Antal

Michelle E Finnefrock

Lisander Lopez

A process to train a machine learning model to predict fault location in a system includes generating a data set for training the machine learning model. The generating includes injecting, at a selected location of the system, a test fault into a simulation of the system using a workload, and recording a respective error syndrome generated by the simulation. Further, the generating includes repeating the injecting, at other selected location(s) of the system, of other test fault(s) into the simulation of the system, and the recording of respective, generated error syndromes. In addition, the process includes training, using the data set, the machine learning model, and providing the trained machine learning model for use in debugging the system, where the debugging includes predicting, using the trained machine learning model, a fault location within the system based on an error syndrome generated by the system due to the fault.

Machine learning model training to assist in system debug

A method for testing a circuit includes performing, by a test engine, a test of bit write to a memory. The test includes defining a bit group based on a set of bits from an address of a memory location. The test further includes generating a bit mask for the bit group. The test further includes performing a bit write operation to the address to store a sequence of bits, the sequence of bits selected using a predetermined bit pattern. The test further includes reading content of the address. The test also includes comparing, using the bit mask, only bits corresponding to the bit group from the sequence of bits and from the content of the address.

Testing bit write operation to a memory array in integrated circuits

A system may include an integrated circuit having repair select bits coupled with a central repair register. The repair register may be configured to determine how to broadcast multiple repair actions to a group of repairable circuits. Inclusion of the repair register may function to reduce the total number of latches used to hold repair information.

Microchip level shared array repair

Pattern recognition is used to proactively treat defects of repeating circuit topologies. A component of a computing environment is monitored for failures. The component includes one or more repeating circuit topologies. A determination is made as to whether a new failure within a repeating circuit topology of the one or more repeating circuit topologies has occurred within a predefined amount of time from a previous failure matching a selected pattern, in which the selected pattern indicates a non-contiguous growing defect. Based on determining the new failure has occurred within the predefined amount of time from the previous failure matching the selected pattern, corrective action for the component is proactively taken.

Pattern recognition for proactive treatment of non-contiguous growing defects

A computer-implemented method includes receiving a memory address of a memory location in a memory that has been identified to be failing. The method further includes determining that the memory location is from a particular portion of the memory. The method further includes, in response to a number of memory locations that are identified to be failing from the particular portion of the memory being below a predetermined threshold, logging the memory address in a set of failing address registers associated with the memory, otherwise, skipping the logging of the memory address in the failing address registers.

Failing address registers for built-in self tests

A method for testing a circuit includes performing, by a test engine, a test of a memory element of the circuit, the test accesses a memory location in the memory element, the memory location is identified by an address, and the memory location is accessed via a first port associated with a first port select bit. The method further includes, in response to detecting a failure associated with the memory location, determining an existing entry for the address in a failed address register, and determining that the existing entry in the failed address register is associated with a second port select bit, distinct from the first port select bit. The method further includes, in response to the second port select bit being distinct from the first port select bit, setting a multi-port failure flag for the memory element that is being tested.

Testing multi-port array in integrated circuits

Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a 'zero' state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the 'zero' state bit and selective transistor biasing, skews the 'zero' state bit towards the complementary &#x201c;one&#x201d; state bit. This induces an increase voltage thresholds of the identified SRAM cells.

SRAM margin recovery during burn-in

Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a 'zero' state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the 'zero' state bit and selective transistor biasing, skews the &#x201c;zero&#x201d; state bit towards the complementary &#x201c;one&#x201d; state bit. This induces an increase voltage thresholds of the identified SRAM cells.

A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ck), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

Global bit line restore timing scheme and circuit

A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

An SRAM design evaluation circuit topology has the gates of the SRAM cell pass Gate Field Effect Transistors (FETs) connected to the cross-coupled gates of the inverter pair of the SRAM cell. This evaluation circuit typology is used in a full cell implementation. A series of full cells are interconnected one to another in a loop to form a ring oscillator. The output of the ring is frequency divided and measured to study the read and write behavior of the cell design. Similarly, half-cells, with the gates of their pass gates grounded, are interconnected one to another to form a ring oscillator, the output of which is frequency divided and measured to help isolate pass gate impact on memory function. The modified SRAM cell topology, connected as a ring oscillator in hardware, can be used to fully characterize an SRAM cell design, without the use of peripheral read/write circuitry.

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Poughkeepsie, NY, United States of America

Uma Srinivasan