International Business Machines Corporation

Ulrike Schmidt

Maarten Jakob Boersma

Udo Krautz

Markus Kaltenbach

Christopher Michael Abernathy

Joerg H Walter

Christopher S Smith

Lothar Felten

Maarten Jokob Boersma

A method detects active power dissipation in an integrated circuit. The method includes receiving a hardware design for the integrated circuit having one or more clock domains, wherein the hardware design comprises a local clock buffer for a clock domain, wherein the local clock buffer is configured to receive a clock signal and an actuation signal. The method includes adding instrumentation logic to the design for the clock domain, wherein the instrumentation logic is configured to compare a first value of the actuation signal determined at a beginning point of a test period to a second value of the actuation signal determined at a time when the clock domain is in an idle condition. The method includes detecting the clock domain includes unintended active power dissipation, in response to the first value of the actuation signal not being equal to the second value of the actuation signal.

Active power dissipation detection based on erroneus clock gating equations

A method for verification of a vector execution unit design. The method includes issuing an instruction into a first instance and a second instance of a vector execution unit. The method includes issuing a random operand into a first lane of the first instance of the vector execution unit and into a second lane of the second instance of the vector execution unit. The method further includes receiving results from execution of the instruction and the random operand in both the first and the second instance of the vector execution unit and comparing the received results.

Verification of a vector execution unit design

A method is provided for verification of a logic design for a processor execution unit which includes an instruction pipeline with one or more pipeline stages. The method includes: creating a design under test using at least a first and a second instance of the logic design; initializing the instruction pipeline using the first instance of the design under test with the same value in each instruction pipeline stage and the second instance with random values in its pipeline stages; selecting an instruction of the processor execution unit out of a plurality of instructions and simultaneously issuing the instruction to each instance of the design under test; providing a comparison between the outputs of the instruction pipeline executing the instruction for each instance; and if the instruction is verifiable by formal model checking, approving the correctness of the logic design if the comparison result is true.

Formal verification of a logic design

The disclosure relates to a test bench, method, and computer program product for performing a test case on an integrated circuit. The test bench may comprise a simulation environment representing an environment for implementing the integrated circuit and a reference model of the integrated circuit, wherein the reference model may be prepared for running within the simulation environment. The test bench may further comprise a device for running a simulation on the reference model within the simulation environment. The reference model may be based on an original reference model provided for a formal verification.

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Boeblingen, Germany

Ulrike Schmidt