Qimonda Ag

Infineon Technologies Ag

Qimonda North America Corporation

Ulrike Gruening-von Schwerin

Thomas Happ

Till Schloesser

Rolf Weis

Jan Boris Philipp

Peter Baars

Franz Kreupl

Stefan Tegen

Klaus Muemmler

Lothar Risch

Ulrich Karl Klostermann

Michael Kund

Klaus-Dieter Ufert

Martin Popp

Ralf Symanczyk

Klaus-Dieter Morhard

Florian Schnabel

Stefan Slesazeck

Bernhard Ruf

Odo Wunnicke

Petra Majewski

Dieter Andres

Wolfgang Henke

Wolfgang Gustin

Wolfgang Mueller

Ulrich Klosterman

Rainer Bruchhaus

Christian Ruester

An integrated circuit includes an array of memory cells. Each memory cell includes a diode. The integrated circuit includes a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of diodes. The integrated circuit includes conductive cladding contacting the doped semiconductor line.

Integrated circuit including doped semiconductor line having conductive cladding

An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.

Array of low resistive vertical diodes and method of production

According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.

Integrated circuit

An integrated circuit having memory cells and a method of manufacture is disclosed. One embodiment provides a switching active volume and a selection transistor coupled in series between a first electrode and a second electrode. The selection transistor is a vertical transistor for at least partially guiding a substantially vertical current flow. The second electrode includes a buried diffused ground plate formed in a substrate. A metal-containing region at least partially contacting the buried diffused ground plate is provided, the metal-containing region at least extending below the selection transistor.

Integrated circuit having memory cells and method of manufacture

An integrated circuit includes transistors in rows and columns providing an array, conductive lines in columns across the array, and resistivity changing material elements contacting the conductive lines and self-aligned to the conductive lines. The integrated circuit includes electrodes contacting the resistivity changing material elements, each electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.

Integrated circuit including a memory fabricated using self-aligned processing

An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.

Integrated circuit including an array of memory cells and method

According to one embodiment of the present invention, an integrated circuit is provided including a plurality of resistivity changing memory elements and a plurality of memory element select devices, wherein the select devices are floating body select devices.

Integrated circuit and method of operating an integrated circuit

A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.

Method of producing an integrated circuit having a capacitor with a supporting layer

A memory includes an array of resistive memory cells, bit lines between rows of the memory cells for accessing the memory cells, and a conductive plate coupled to each of the memory cells.

Thermal isolation of phase change memory cells

In a method for fabricating a semiconductor component, a semiconductor substrate comprising a first surface is provided and a shaping matrix is applied to the first surface. The shaping matrix comprises at least one continuous depression arranged in such a way that contact regions in a region of the first surface are at least partly uncovered. A sacrificial layer is applied to sidewalls of the continuous depression in an upper section of the depression, a first electrode is produced by applying a first conductive layer in a lower section of the depression and to the sacrificial layer, and the sacrificial layer is removed in order to uncover the sidewalls of the shaping matrix in the upper section. A dielectric layer is applied to the first conductive layer and a second electrode is formed by applying a second conductive layer to the dielectric layer.

Method for fabricating a semiconductor component and semiconductor component

An integrated circuit includes a contact, a first spacer, and a first electrode including a first portion and a second portion. The second portion contacts the contact and is defined by the first spacer. The integrated circuit includes a second electrode and resistivity changing material between the second electrode and the first portion of the first electrode.

Integrated circuit including spacer defined electrode

An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25&#x2266;DL/DC&#x2266;1/1.75.

Integrated circuit having a memory cell array and method of forming an integrated circuit

A memory includes an array of memory cells, each memory cell including resistive material, a first insulation material laterally surrounding the resistive material of each memory cell, and a heat spreader between the memory cells to thermally isolate each memory cell.

Integrated circuit having resistive memory cells

An integrated circuit, a memory cell, memory device and method of operating the memory device is disclosed. In one embodiment, an integrated circuit having a resistively switching memory cell includes a bitline electrode and a second electrode having a lower voltage potential than the bitline electrode; a switching active volume and a selection transistor connected in series between the bitline electrode and the second electrode. The second electrode is connected, via a connection transistor, to a third electrode having the same or a lower voltage potential than the second electrode; wherein the second electrode includes a buried electrode at least partially positioned below the bitline electrode and the third electrode.

Integrated circuit having a resistive switching device

A memory includes transistors in rows and columns providing an array and conductive lines in columns across the array. The memory includes phase change elements contacting the conductive lines and self-aligned to the conductive lines. Each phase change element is coupled to one side of a source-drain path of a transistor.

Growing community of inventors

Munich, Germany

Ulrike Gruening-von Schwerin