Other

International Business Machines Corporation

Infineon Technologies Ag

Infineon Technologies North America Corp.

Siemens Aktiengesellschaft

Siemens Aktiengesell Schaft

Qimonda Ag

Ulrike Gruening

Jack Allan Mandelman

Carl John Radens

Ramachandra Divakaruni

Jochen C Beintner

Helmut Horst Tews

Gary Bela Bronner

Gerhard Mueller

Alexander Michaelis

Rajarao Jammy

Johann Alsmeier

Johnathan E Faltermeier

Larry Alan Nesbit

Stephan Kudelka

Thomas S Rupp

Brian S Lee

Uwe Paul Schroeder

Zvonimir Gabric

Dirk Tobben

Oswald Spindler

Hans-Oliver Joachim

Raj Jammy

David V Horak

Toshiharu Furukawa

Paul Christian Parries

Rama Divakaruni

Wolfgang Bergner

Christopher Carr Parks

Suryanarayan G Hegde

Paul Andrew Ronsheim

Young-Jin Park

Susan E Chaloux

Gill Lee

Jeffrey P Gambino

Till Schloesser

Tze-Chiang Chen

John Kenneth DeBrosse

Yun-Yu Wang

Byeong Yeol Kim

Scott David Halle

Helmut Klose

Frank Jakubowski

Rajesh Rengarajan

Jeffrey John Welser

Satish D Athavale

Jürgen Faul

Rainer Florian Schnabel

Thomas Schuster

Jean-Marc Rousseau

Akira Sudo

Jürgen Amon

Rudolf Strasser

Juergen Wittmann

Giuseppe LaRosa

Ranier Florian Schnabel

Stephen Kudelka

John Faltermeier

Martin Schrems

Carl Radens

The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS, GS, GS, GS) on a semiconductor substrate (), having the following steps: application of the gate stacks (GS, GS, GS, GS) to a gate dielectric () above the semiconductor substrate (); formation of a sidewall oxide () on sidewalls of the gate stacks (GS, GS, GS, GS); application and patterning of a mask () on the semiconductor structure; and implantation of a contact doping () in a self-aligned manner with respect to the sidewall oxide () of the gate stacks (GS, GS) in regions not covered by the mask ().

Method for fabricating a semiconductor structure

An improved sub 8F memory cell is disclosed. The sub 8F cell includes a shallow transistor trench in which a buried portion of the transistor occupies.

Trench capacitor memory cell

A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.

Field-shield-trench isolation for gigabit DRAMs

A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.

Self-aligned near surface strap for high density trench DRAMS

A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the < > crystallographic plane and another one of such planes being the < > plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the < > plane being oxidized at a higher rate than sidewalls in the < > plane producing silicon dioxide on the silicon nitride layer having thickness over the < > plane greater than over the < > plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the < > plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the < > plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the < > plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the < > plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.

Semiconductor structures and manufacturing methods

A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M metallization layer.

Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect

A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.

Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch

A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the <100> crystallographic plane and another one of such planes being the <1 10> plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the with substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the <110> plane being oxidized at a higher rate than sidewalls in the <100> plane producing silicon dioxide on the silicon nitride layer having thickness over the <110> plane greater than over the <100> plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the <100> plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the <110> plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the <100> plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the <110> plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.

Sensing of information from a memory cell via a plateline is disclosed. The memory cell comprises a bitline coupled to a junction of a cell transistor while the other junction is coupled to an electrode of the capacitor. The bitline is coupled to a constant voltage source. A plateline is coupled to the other capacitor electrode.

Memory cell for plateline sensing

A semiconductor memory cell, in accordance with the present invention includes a deep trench formed in a substrate. The deep trench includes a storage node in a lower portion of the deep trench, and a gate conductor formed in an upper portion of the deep trench. The gate conductor is electrically isolated from the storage node. An active area is formed adjacent to the deep trench and is formed in the substrate to provide a channel region of an access transistor of the memory cell. A buried strap is formed to electrically connect the storage node to the active area when the gate conductor is activated. A body contact is formed opposite the deep trench in the active area and corresponding in position to the buried strap to prevent floating body effects due to outdiffusion of the buried strap. Methods for forming the body contact are also described.

Structure and method for forming a body contact for vertical transistor cells

A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conductor of the storage capacitor. A layer of silicon is deposited over the barrier material. Dopant ions are implanted at an angle into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

Single sided buried strap

A semiconductor device formed by a method for aligning a strap diffusion, in accordance with the invention, includes the steps of providing a trench in a substrate, the trench having a storage node formed therein including a buried strap on top of the storage node, and depositing a dopant rich material on the buried strap. A trench top dielectric is formed on the dopant rich material, and portions of the dopant rich material are removed above the trench top dielectric. Dopants are outdiffused from the dopant rich material into an adjacent region of the substrate to form the strap diffusion by forming a gate in an upper portion of the trench such that the strap diffusion is operatively disposed relative to the gate.

Self-aligned buried strap for vertical transistors

A dynamic random access memory (DRAM) formed in a silicon chip that includes a support area in which support circuitry of the memory includes a single electrical contact through two dielectric layers to a conductive layer of a gate stack of a field effect support transistor that has a capping layer through which the electrical contact passes to the gate. The DRAM also includes a memory area containing an array of memory cells each include a field effect transistor. Drain regions of the transistors of the memory cells and drain and source regions of field effect transistors of the support transistors have first electrical contacts thereto through the first dielectric layer and have second electrical contacts which pass through the second dielectric layer and electrical contact to the first electrical contacts. Forming of the second electrical contacts concurrently with the single electrical contact to the gate of the support transistor saves a processing step over prior art processes.

Dynamic random access memory

A method of using at least two insulative layers to form the isolation collar of a trench device, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide ) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer ( ) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate ( ) doping.

Integrated circuit trench device with a dielectric collar stack, and method of forming thereof

A process for forming a buried strap self-aligned to a deep storage trench. Spacers are formed on walls of a recess over a filled deep trench capacitor and a substrate. A plug is formed in a region between the spacers. Photoresist is deposited over the spacers, the plug, and material surrounding the spacers of the plug. The photoresist is patterned, thereby exposing portions of the plug, the spacers, and the surrounding material. The spacers in the surrounding material not covered by the photoresist are selectively etched, leaving a remaining portion of the spacers. The substrate and the portion of the filled deep trench exposed by the spacer removal are selectively etched. An isolation region is formed in a space created by etching of the spacers, surrounding material, substrate, and filled deep trench.

Process for buried-strap self-aligned to deep storage trench

Growing community of inventors

Munich, Germany

Ulrike Gruening