Infineon Technologies Ag

Heliatek Gmbh

Fraunhofer-gesellschaft Zur Foerderung Der Angewandten Forschung E.v.

Qimonda Ag

Ulrike Bewersdorff-Sarlette

Danny Pak-Chum Shum

Manfred Schneegans

Karl Leo

Christoph Ludwig

Stephan Wege

Martin Pfeiffer

Clemens Fitz

Christoph Kleint

Wolfram Langheinrich

Werner Graf

John Power

Lars Mueller-Meskamp

Christian Uhrich

Alfred Vater

Martin Pfeiffer-Jacob

John Fahlteich

Moritz Riede

David Pritchard

Nicole Prager

Hocine Boubekeur

Lars Müller-Meskamp

Sylvio Schubert

Jan Meiss

Torsten Müller

Wolfgang Jäger

Michiel Top

Jan Meiß

When organic photovoltaic components are laser-structured, protuberances occur, which can protrude significantly beyond the height of the layered stack. The invention describes a technique for stabilising the laser-structured protuberances so that further processing of the semi-finished product is possible, and describes the integration of said product in a subsequent encapsulation of the OPV component.

Stabilization of laser-structured organic photovoltaics

An optoelectronic component on a substrate includes a first and a second electrode. The first electrode is arranged on the substrate and the second electrode forms a counter electrode. At least one photoactive layer system is arranged between these electrodes. The at least one photoactive layer system including at least one donor-acceptor system having organic materials.

Transparent electrode for optoelectronic components

In one embodiment, a method of forming a semiconductor device is disclosed. A high-k dielectric is deposited of over a semiconductor body, and a portion of the high-k dielectric is wet etched an etchant selected from the group consisting of hot phos, piranha, and SC1.

Method of forming a non volatile memory device using wet etching

A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.

Buried bitline with reduced resistance

A gate structure of a transistor is fabricated with an additional barrier formed on a metal layer of the gate structure before the deposition of a silicon oxide layer. Applying this barrier layer on the metal layer before the deposition of the silicon oxide layer prevents an oxidation of the metal during the deposition of the silicon oxide layer. A lowering of the conductivity of the metal layer or a loss of metal through sublimating metal oxide is thereby prevented. As a result, in particular the performance of the gate structure or of the transistor is improved further. In addition, disturbing coupling effects in the circuit are significantly reduced by the use of the silicon oxide cap.

Method for fabricating a transistor with a gate structure

A method for fabricating a semiconductor component includes: deposition of a polysilicon layer on a substrate, deposition of a precursor layer on the polysilicon layer, and deposition of a protective layer on the precursor layer. A crystalline transformation occurs in the precursor layer at a first temperature to form an electrode layer. The layers are patterned to form an electrode stack, and the polysilicon layer is oxidized at a second temperature such that no crystalline transformation occurs in the electrode layer.

Production method for a semiconductor component

Growing community of inventors

Radebeul, Germany

Ulrike Bewersdorff-Sarlette