Infineon Technologies Ag

Infineon Technologies Richmond, LP

Qimonda Ag

Ulrich Zimmermann

Armin Kohlhase

Andreas Rusch

Yoichi Otani

Michael Bernhard Sommer

Joerg Vollrath

Thomas B&ouml;hm

Joerg W Wohlfahrt

Dieter Rathei

Robert Petter

Manfred Hain

Philip R Moore

Alexander Trueby

Mark E Luzar

Ralf Gerber

Babatunde Ashiru

Steffen Rothenhäusser

Thomas S Taylor

Luis G Andrade

Alexander Tr&uuml;by

Thomas Achammer

The invention relates to a semiconductor memory, and to a measuring method for a semiconductor memory. In one case, the method includes connecting a memory cell to a ring oscillator and measuring the frequency resulting for said ring oscillator.

Measuring method for a semiconductor memory, and semiconductor memory

A DRAM semiconductor memory device with increased reading accuracy and a method for increasing the reading accuracy of a DRAM memory cell are provided. First and second bit lines are connected to a sense amplifier and are connected in each case to a further memory cell. The gates of the further memory cells are driven via a driving circuit device. An equalization voltage of the two bit lines is influenced in the event of a precharge operation, and a capacitive disequilibrium is avoided at inputs of a sense amplifier due to the voltages on the bit lines in the event of reading the memory cell.

DRAM semiconductor memory device with increased reading accuracy

A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.

Method of making a semiconductor memory device

A current measurement circuit and method for testing a semiconductor device is provided. The method includes the steps of providing a semiconductor integrated circuit device including a voltage regulating circuit, the voltage regulating circuit being activated as needed to maintain a required voltage level; monitoring the voltage regulating circuit to determine a number of times it is activated during a sample period; and comparing the number of activations to a predetermined limit whereby if the number of activations exceeds the predetermined limit the semiconductor device is defective. The current measurement circuit includes an external clock for providing a clock signal; a first counter for counting when the voltage regulating circuit is activated; a second counter for counting clock cycles of a sample period; and a register for storing the number of activations, wherein the number of activations represents a relative current consumption value of the semiconductor device.

Current measurement circuit and method for voltage regulated semiconductor integrated circuit devices

A method of calculating yield loss of semiconductor wafers which are tested with a test sequence to derive a total fail region count for each of the wafers, the semiconductor wafers having multiple chips thereon. The method comprises calculating a fail region count for each of the tests in the test sequence, calculating the test sequence limited yield loss for each of the wafers, and apportioning the test sequence limited yield loss to selected ones of the test based upon the absolute or cumulative number of fails identified by the tests of the test sequence. In some embodiments, core parametric test data is correlated with the test sequence limited yield and analyzed to determine reparability.

Method for semiconductor yield loss calculation

The memory cell configuration has a large number of memory cells provided in a semiconductor substrate and having bit-line trenches which extend in parallel in the longitudinal direction in the main face of the semiconductor substrate, at the bottoms of which in each case a first conductive region is provided, at the peaks of which in each case a second conductive region of the same conduction type as the first conductive region is provided, and in the walls of which in each case an intermediately located channel region is 0 provided; and having word lines which extend in the transverse direction along the main face of the semiconductor substrate, through specific bit-line trenches, to activate transistors provided there. An additional dopant is introduced into the trench walls of the bit-line trenches which are located between the word lines, in order to increase the corresponding transistor turn-on voltage there to suppress leakage currents.

Memory cell configuration and corresponding production process

A semiconductor read-only memory (ROM) has trenches and vertical transistors. The trenches are filled with insulator material during the manufacturing process. Holes, which are as wide as the trenches are etched into the insulator at regions where word lines and decoder lines are to be provided over the trenches in a later manufacturing step. In a subsequent masking process for changing the conductivity characteristic of channel regions of transistors, channel regions selected according to programming requirements, are doped. The insulator remaining in the trenches prevents that regions under the insulator material are affected by the masking method.

Semiconductor read-only memory and method of manufacturing the same

A semiconductor device includes a plurality of bitlines arranged in an array, the plurality of bitlines being grouped in pairs and at least some of the bitlines include a twist. A twist region is disposed along the plurality of bitlines wherein the twist region occupies layout area designated for the twists. An equalizer element is disposed in the twist region for equalizing a pair of bitlines.

Bitline twist with equalizer function

A read-only memory cell array has vertical MOS transistors formed on trench walls, and is programmed with a programming mask which covers only the areas at which a transistor is not to be produced. As a result, the word lines can be formed with minimum grid spacing and the risk of short-circuiting between adjacent word lines is eliminated by buried ploy stringers.

Read-only memory cell array and method for fabricating it

A trench capacitor cell, in accordance with the present invention, includes a trench having an outer electrode formed in a substrate adjacent to the trench. A storage node is formed in the trench and capacitively coupled to the outer electrode. A center node is capacitively coupled to the storage node, and the storage node surrounds the center node within the trench. The center node includes a portion extending from the trench for connecting to a potential to provide charge retention in the storage node during operation.

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Mechanicsville, VA, United States of America

Ulrich Zimmermann