Infineon Technologies Richmond, LP

Ulrich Zimmerman

Robert Petter

Robert Trahan

Allen Chu

A fuse configuration for a semiconductor storage device is provided. The fuse configuration includes a first electrode formed in a dielectric layer, the first electrode having a first cross-sectional area defined by a first perimeter; a fuse element, or isolating layer, for coupling the first electrode to a second electrode; and the second electrode having a second cross-sectional area defined by a second perimeter, the first perimeter of the first electrode being larger than the second perimeter. By employing this modified capacitor layout, the fuse element, or isolating layer, will never come into contact with an edge of the first electrode, and thus eliminate a high electric field region from the fuse layout and reliability issues of the prior art fuse configurations. A method for forming the fuse configuration is also provided.

Fuse configuration with modified capacitor border layout for a semiconductor storage device

A system and method for determining the accuracy of the states of fuses by changing, or not changing, the state of additional fuses. The system includes a memory including addressable storage elements, address fuses whereby each fuse includes a link in a connected or disconnected state and the collective state of the address fuses identifies an address value, a parity fuse whereby the fuse includes a link in a connected or disconnected state and the state of the parity fuse represents a parity value, the parity value being based on, but not equivalent to, the address of an addressable storage element, and; an output providing a value dependant upon the address value and the parity value.

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Ottendorf-Okrilla, Germany

Ulrich Zimmerman