International Business Machines Corporation

Ulrich Weiss

Tobias Webel

Scott Barnett Swaney

Kenneth Lundy Ward

Matthias Woehrle

Rolf Sautter

Thomas Pflueger

Wilhelm Ernst Haller

Dietmar Schmunkamp

Christoph W Wandel

Daniel Mark Dreps

Frank David Ferraiolo

Pak-kin Mak

Peter Anthony Sandon

Erich Klink

Gerard M Salem

Hubert Harrer

Roland Frech

Andreas Wagner

Thomas-Michael Winkel

Tobias Ulrich Bergmann

Cédric Lichtenau

Rolf B Hilgendorf

Thomas Makowski

Jens Kuenzer

Bernd Leppla

William Frederick Shutler

Florian Braun

Ching-Lung L Tong

Ralf Ludewig

Guenter Knauft

Friedhelm Kessler

Mathew I Ringler

Harald Mielich

Dana J Thygesen

Wilhelm Schmits

Reinhold Ludwig

Martin Boertzel

Dedric Lichtenau

Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and in an asynchronous mode when the variable frequency is lower than the fixed frequency. A first buffer and a second buffer are used for a data transfer from the first clock domain to the second clock domain. The second clock domain comprises a multiplexor connected to the first buffer and the second buffer. The multiplexor forwards data from the first buffer further into the second clock domain in the synchronous mode and from the second buffer into the second clock domain in the asynchronous mode.

Low latency data transfer between clock domains operated in various synchronization modes

A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.

Synchronous clock stop in a multi nodal computer system

A method includes removing a code segment from a hardware description language design to create a modified hardware description language design. The code segment represents at least one time sensitive path in the hardware description language design. The method includes creating a delta list of differences between the modified hardware description language design and a physical hardware representation that is logically equivalent to the hardware description language design. The method includes extracting a portion of the physical hardware representation that corresponds to the time sensitive path based, at least in part, on the delta list. The method also includes creating a structured hardware description language design of the time sensitive path using the extracted portion of the physical hardware representation, wherein the structured hardware description language design comprises structural information of the extracted portion of the physical hardware representation.

Reusable structured hardware description language design component

A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input () to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

Adder structure with midcycle latch for power reduction

Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

Fault tolerant time synchronization mechanism in a scaleable multi-processor computer

Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer

The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.

Signal delay element, method and integrated circuit device for frequency adjustment of electronic signals

A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage with static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input () to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) () and the wiring () from there to multiple, PLL-() free clock chips () is provided. Instead of only one DCSC () and one single wiring (), two of them (----) are used combined with a further particular logic present on each clock chip (), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.

Redundant oscillator distribution in a multi-processor server system

A method, apparatus, and computer program product in a data processing system for testing differential clock or oscillator signals. A method is comprised of the following steps: A first single-ended receiver is connected to a positive leg of a differential pair, and a second single-ended receiver is connected to a negative leg of the differential pair. An output of the first single-ended receiver is inverted and delayed before being input into a first RS Flip-Flop. An output of the second single-ended receiver is delayed before being input into a second RS Flip-Flop. An output of a differential receiver is inverted and input into the first and second RS Flip Flops as reset signals. Then a Wire OK signal is output indicating the condition of the legs of the differential pair.

Eclipz wiretest for differential clock/oscillator signals

A synchronization system capable of simultaneously resetting frequency divide-by counters () of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal ()) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit () for each processor that simulates in the undivided signal (Mclk/1 signal ()) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal () and sends an asynchronous offset signal () to a counter re-setter () that resets the divide-by counter to zero based on the offset signal.

System and method for synchronizing divide-by counters

Described is a novel implementation of a medium and high frequency on-module (off-chip)/on-chip power noise filter for power noise sensitive circuits. To achieve this, a second order low-pass approach is used. The first stage capacitor is located on-module (off-chip), and the second stage capacitor is implemented on-chip.

Two-stage power noise filter with on and off chip capacitors

An electrical circuit for generating clock pulses for a multi-chip computer system which contains a clock generation chip and various logic circuit chips. The clock pulses used on the logic circuit chips are generated on the clock generation chip and are transferred to the logic circuit chips. For the generation of the clock pulses a so-called clock splitter circuit is provided on the clock generation circuit. This clock splitter generates two pulse strings out of a third pulse string which is derived from an oscillator. The clock splitter contains a number of gates and latches which have an impact on the throughput time of a pulse to run through the clock splitter, as well as on the skew of the two generated pulse strings. The invention provides an electrical circuit which has an improved throughput time and skew of the generated pulse strings.

Electrical circuit for generating pulse strings

A regulator includes a switching transformer (TR) whose primary winding is divided into two halves through which current flows alternatingly via one respective switching transistor (Q1, Q2). The pulses on the secondary side of the transformer are rectified to attain the output voltage. The output voltage is controlled by pulse width modulated driver pulses for the two switching transistors. A protective circuit (12) with immediate effect terminates the currently applied driver pulse when the current flowing through the conductive switching transistor reaches a critical current value. A protective circuit (14) with delay effect prevents the generation of further driver pulses upon a further increased overload, this prevention being limited with respect to time. The protective system directly is controlled by the primary current of the power regulator.

Power regulator with overcurrent protection

Growing community of inventors

Holzgerlingen, Germany

Ulrich Weiss