Deutsche Itt Industries Gmbh

Micronas Gmbh

Itt Manufacturing Enterprises, Inc.

Micronas Semiconductor Holding Ag

Ulrich Theus

Mario Motz

Juergen Kessel

Burkhard Giebel

Reiner Bidenbach

Martin Czech

Soenke Mehrgardt

Lothar Blossfeld

Arnold Uhlenhoff

Andreas Menkhoff

Heinrich Pfeifer

Werner Reich

Norbert Greitschus

Eckart Wagner

Hans-Josef Orben

Paul O'Leary

Juergen Niendorf

Peter Lee

Jürgen Kessel

A method and circuit arrangement is provided for controlling switching transistors of an integrated circuit, with a bridge circuit and with a control unit, which is designed and/or has a program so that the control unit is designed as a measuring device and measures a bridge voltage of the bridge circuit, outputs an adjusting signal for adjusting a component of a bridge circuit, and outputs a control signal for activating the switching transistors. When the bridge circuit) has a branch with a resistor network and a transistor connected in series, and the control unit is designed and/or has a program so that the adjusting signal for adjusting a resistance value of the resistor network is switchable as the component dependent on the bridge voltage.

Method and circuit arrangement for controlling switching transistors of an integrated circuit

A CMOS output stage operates in A/B push-pull mode and is driven with a control potential (ud) from a preamplifier stage via a control line (st). The control line (st) feeds the gate terminals of a complementary transistor pair (kt), the first transistor (n) of which is used as first push-pull output transistor and the second transistor (p) of which is connected to the gate terminal of a second push-pull output transistor (pa) via a current balancing arrangement. The source terminal of the first and of the second transistor (n, p) is connected to a first and, respectively, to a second fixed potential (u, u), the second fixed potential (u) being stabilised in a low-impedance manner by an active compensation circuit (K).

Three-stage amplifier

A two-stage amplifier includes a first stage and a second stage that are DC-connected through a coupling capacitor Cp. A charge pump generates a bias voltage Vp that is applied across the coupling capacitor Cp leads to maintain the time average of the voltage across said coupling capacitor constant.

Two-stage amplifier

To protect against electrostatic discharges in monolithic integrated circuits in CMOS technology, a lateral thyristor structure is presented which has a much lower firing voltage compared to conventional thyristor structures.

Lateral thyristor structure for protection against electrostatic discharge

To detect a fault state due to a line break in power supply lines on the receiving side during the operation of a transducer device, the transducer output voltage is forced to an extreme voltage range by a co-integrated p-channel-depletion-transistor. As a result, the signal detection device can reliably detect the presence of the fault state due to a line break in the supply feed lines.

Electronic transducer device

In integrators which integrate the analog photocurrent of a photodiode (PD), the amplification-bandwidth product is relatively small on account of the parallel parasitic capacitance (Cp) of the photodiode (PD). However, in a design with a switched capacitor (C ), the bandwidth and at the same time the DC amplification must be large, so as to assure the integrator function even at low frequencies. So as to fulfill both of these mutually contradictory requirements for large bandwidth and high DC amplification, a reference voltage (V ) is present at a voltage divider that includes a resistor (R ) and a circuit section (R ) connected in series thereto, as well as at the photodiode (PD). The connection point of the voltage divider is connected to the inverting input of the transconductance amplifier (V). In a preferred embodiment, the circuit section (R ) is realized as a switched capacitor (C ), and the resistance (R ) is realized as an MOS transistor (T ). As an integrated switching circuit, the invention is especially suited for sigma-delta-analog converters.

Analog integrator circuit

A function generator includes a switching stage for forming a defined signal waveform. The switching stage includes switching transistors that are turned on in a predetermined sequence of undelayed and delayed clock signals, with an output node summing the output currents of the switching transistors. The function generator also includes a delay device that generates the undelayed and delayed clock signals from an applied clock signal. The delays of the delayed clock signals define predetermined instants within at least one period of the applied clock signal. The switching edge is divided into different time ranges whose respective edge steepnesses are adjustable independently of each other. By point-mirroring the signal waveform about a medium value of the signal edge, frequencies at twice, four times, six times, etc. the frequency of the fundamental signal frequency are reduced. Due to the sinusoidal shape of the switching edges, electromagnetic emissions are reduced because of the reduced amplitude of the harmonics. The electromagnetic emission reduction applies both to pure clock signals and to other digital signals, including control, data, or supply lines.

Signal generator

Spurious-emission-reducing terminal configuration for an integrated circuit, particularly a monolithic integrated circuit, operable within an unshielded board network, the integrated circuit being divided into a first subcircuit, which has essentially radio-frequency current components, and a second subcircuit, which has essentially low-frequency current components, the separation also extending to the internal supply lines and supply contact pads. The second subcircuit includes driver circuits which are connected to I/O lines on the board network. On the grounded side, the first and second supply current paths are interconnected within the integrated circuit by a low-resistance and low-inductance connection to establish a ground point.

Spurious-emission-reducing terminal configuration for an integrated

A monolithic integrated sensor circuit is disclosed comprising a sensor system for generating an electronic sensor signal; a supply unit for the sensor system; an amplifying stage for amplifying the sensor signal; a plurality of inverting devices in the signal path of the amplifying stage which reverse the polarity of the sensor signal at equal time intervals, the time intervals and inversion of the sensor signal being controlled by a clock signal source; and an averaging combiner stage whose input receives an amplified sensor signal and whose output has a reference polarity which is controlled by means of the inverting devices in such a way as to be always the same regardless of the switching state in the signal path. The monolithic integrated sensor circuit of the present invention minimizes the offset error.

Monolithic integrated sensor circuit

The invention relates to a digitally adjustable crystal oscillator having a quartz crystal and a monolithic integrated oscillator circuit including a series combination of a first frequency-adjusting capacitor C1 and a second frequency-adjusting capacitor C2 connected in parallel with the quartz crystal and comprising parallel-connected first capacitance stages and parallel-connected second capacitance stages, respectively, and an inverter circuit connected in parallel with the quartz crystal and comprising a feedback resistor R.sub.K, the output of the innverter circuit being connected to a load resistor. The inverter circuit comprises parallel-connected inverter stages, and switching elements are provided within the inverter stages and cqapacitor stages in such a way that a respective one of the inverter stages as well as a first capacitance stage C.sub.1i and a second capacitance stage C.sub.2i are switchable into or out of circuit by means of a control signal I.sub.i.

Digitally adjustable crystal oscillator with a monolithic integrated

A monolithic integrable mixer network for a mixer console includes a variable gain preamplifier for each sound channel, a summing amplifier whose summing gain is adjustable differently for each sound channel, and a control unit which divides the channel gain for the respective sound channel between the preamplifier and the summing amplifier according to a ratio dependent on the desired channel gain to optimize the noise performance of the mixer network.

Monolithically integrable mixer network for a mixer console

A clock generator circuit for clock controlled electronic devices, which causes minimal electromagnetic interference in adjacent electronic equipment. The clock generator circuit includes a clock source for generating a basic clock signal having a predetermined frequency. The basic clock signal defines a reference clock signal having a period T. A phase modulator coupled to the clock source for producing a system clock signal by delaying the basic clock signal. A signal source coupled to the phase modulator, which controls the phase modulator so that the system clock signal is delayed with respect to the reference clock signal by a time period less than half of the period T of the reference clock signal.

Clock generator for generating a system clock causing minimal

A current mirror circuit including at least one current bank transistor coupled to a cascade transistor. The cascade transistor further coupled to a current mirror input. A current-controlled current source operable for both receiving a differential current from said current mirror input and for producing a charging current for charging a gate of the at least one current bank transistor in order to null the differential current.

Current mirror in MOS technology comprising cascade stages with wide

The invention relates to a magnetic-field sensor with a Hall effect device, a power supply, and an evaluating facility, which can be supplied with a Hall signal from the Hall-effect device and comprises an input amplifier, a storage element, and a signal superposition unit. To improve the accuracy of the magnetic-field sensor, in a first phase, a balancing signal for balancing the measurement-signal path with respect to an interface can be produced with the evaluating facility, the balancing signal being storable in the storage element, and in a second phase, the balancing signal stored in the storage element can be applied through the signal superposition unit to the interface, where it is superimposed on a Hall signal.

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Gundelfingen, Germany

Ulrich Theus