Siemens Aktiengesellschaft

Ulrich Ramacher

Karl Knauer

Juergen Pandel

Hans-Joerg Pfleiderer

Wolfgang Raab

Joerg Beichter

Ulrich Hachmann

Jorg Beichter

Nikolaus Bruls

Jorg Gliese

Alexander Schackow

Rene Schuffny

Image-processing processor

Circuit arrangement for calculating matrix operations in signal

A digital neural network has a plurality of neurons (NR) completely meshed with one another, each of which comprises an evaluation stage having a plurality of evaluators (B) that is equal in number to the plurality of neurons (NR) and each of which comprises a decision stage having a decision unit (E). An adjustment information (INF.sub.E) that effects a defined pre-adjustment of the decision unit (E) can be supplied to every decision unit (E) by a pre-processing means via an information input. A weighting information (INF.sub.G) can be supplied to every evaluator (B) by a pre-processing means via an individual information input. An output information (INF.sub.A) can be output by every decision unit (E) to a post-processing means via a respective individual information output. The information outputs of the decision units (E) are each connected to an individual processing input of all evaluators (B) allocated to the appertaining decision unit (E). Individual processing outputs of the evaluators (B) are connected to individual processing inputs of the decision unit (E) in the appertaining neuron (N), so that every output information (INF.sub.A) can be indirectly fed back onto every neuron (NR).

Digital neural network executed in integrated circuit technology

A network architecture for the programmable emulation of large artificial neural networks ANN having digital operation employs a plurality L of neuron units of identical structure, each equipped with m neurons, the inputs (E) thereof being connected to network inputs (E.sub.N) multiplied or branching via individual input registers (REG.sub.E). The outputs (A) of the neuron units are connectable to network outputs (A.sub.N) at different points in time via individual multiplexers (MUX) and individual output registers (REG.sub.A) and the neuron units have individual auxiliary inputs via which signals can be supplied to them that represent weighting values (W) for weighting the appertaining neural connections and represent thresholds (0) for weighting input signals.

Network architecture for the programmable emulation of artificial neural

In discrete wafer-scale integration abbreviated as WSI, pre-tested chips are mounted and bonded on a pre-wired wafer. Silicon usually serves as the wafer substrate because the wafer wiring can be cost-beneficially produced with a standard multi-layer process. The conducting properties of such a wafer micro-wiring forbid the use of long leads given high timing clocks, so that intermediate drivers must be utilized. Previous solutions make use of separate driver chips that must be placed, bonded and tested in addition to the actual function chips. In the disclosed WSI system, the intermediate drivers are not realized as separate chips but are implemented on the function chip itself.

On-chip intermediate driver for discrete WSI systems

A method and apparatus for the production of a test-compatible, largely defect-tolerant configuration of redundantly implemented, systolic VLSI systems. The method and apparatus for the configuration of redundantly implemented, systolic VLSI systems meets the conditions of defect-tolerance, test-compatibility and minimum hardware requirement. For this purpose, every module of the multi-dimensional systolic VLSI system has control logic allocated to it which controls A, B and C switches for the appertaining module. It is possible with the use of these switches to bridge a maximum of up to two faulty modules per row and one faulty module per column. A configuration algorithm provides a determination as to whether the established VLSI system is in the position to be able to execute the desired arithmetic operations.

Method and apparatus for manufacturing a test-compatible, largely

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Munich, Germany

Ulrich Ramacher