International Business Machines Corporation

Ulrich Olderdissen

Manfred Walz

Hans Schumacher

Horst E Barsuhn

Werner Schmidt

A data mechanism having a random access memory (RAM) which has a plurality of groups of memory chips, each group being divisible into two equally sized chip sets. Each group of memory chips is addressed by a first address and each individual memory chip is addressed by a second address. The random access memory contains stored data. A cache, connected to the RAM, stores a portion of data stored in the RAM and is accessed by a cache address for separately reading requested data therefrom. The cache provides a cache miss signal when it does not contain the requested data. A CPU, connected to the cache and the RAM, receives the cache miss signal and provides responsive thereto, a starting address to the random access memory for starting a block transfer from the random access memory to the cache in two shots. The starting address includes the first address and the second address. The starting address identifies the group and individual chip within the group which contains the first bit which, when attempted to be read from the cache, caused the cache miss signal. A decoder, connected to the CPU and the random access memory, receives the starting address from the CPU and enables a first block data transfer from a first chip set in a first shot of the two shots starting from said first bit which caused the cache miss signal, and further enables a second block data transfer from a second chip set in a second of the shots.

DRAM chip and decoding arrangement and method for cache fills

Decoding of BCH multiple error correction code codewords with .alpha. as a primitive element of the finite field GF (2.sup.m) is accomplished by generating syndrome subvectors S.sub.1 from all column m-tuple .alpha..sup.k positions and syndrome subvectors S.sub.2 from all column m-tuple .alpha..sup.3K positions, generating a permutation of syndrome subvector S.sub.1 for each bit position on the codeword and then selecting those bit positions K where S.sub.1.sup.3 +S.sub.2 +QK=0 as the bit or bits in error.

Decoding of BCH double error correction - triple error detection

This specification describes transferring a partial block of data with first and last words that are partial words from a processor and storing it in a memory protected by an error correcting code that requires the words to be stored in the memory as whole words. Prior to the initiation of the transferring and storage procedure, the memory is accessed and data words corresponding to the partial words in the partial block of data are fetched and placed in registers. Thereafter, during the transferring of the partial words, the fetched words are combined with the partial words to generate full words. Error correction check bits are added to these generated full words and the combination is stored into the memory.

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Herrenberg, Germany

Ulrich Olderdissen