Nxp B.v.

Nxp Usa, Inc.

Trident Microsystems (far East) Ltd.

Alcatel Lucent

Ulrich Moehlmann

Andreas Johannes Köllmann

Jan-Peter Schat

Cristian Pavao Moreira

Christian Scherner

Edwin Jan Schapendonk

Andreas Lentz

Leendert Albertus Dick Van Den Broeke

Steffen Rode

Michael Linne

Ralf Gero Pilaski

Lars Henrik Heinbockel

Tim Lauber

Kai Hendrik Misselwitz

Torsten Gerhardt

Felix Naethe

Andreas Szaj

Timo Giesselmann

Frank Brand

Christian Polatschek

Martin Grasberger

Jens Blankenhorn

Franck Schaich

Christian Moegle

Stephanie Hantke

A system includes a phase-shift to duty-cycle converter and a low pass filter. The phase-shift to duty-cycle converter has a first input for a reference clock and a second input for a phase-shifted clock that is phase-shifted relative to the reference clock. The low pass filter has an input coupled to an output of the phase-shift to duty-cycle converter and an output for an output signal. In some implementations, the phase-shift to duty-cycle converter includes a simple logic gate and a reset-set flip flop. The simple logic gate has a third input coupled to the first input and a fourth input coupled to the second input, and the reset-set flip flop has a fifth input coupled to the first input and a sixth input coupled to the second input. The low pass filter is coupled to the output of one of the simple logic gate and the reset-set flip flop.

Analog phase selection test system

Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system () comprising a plurality of radar transceiver modules () mounted to a common PCB (), the plurality of radar transceiver modules comprising a leader module () and one or more follower modules (), the leader module () comprising a first oscillator () configured to provide a first clock signal at a first frequency to each follower module (), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (), the PLL clock signal generator () comprising a divide by n clock divider () arranged to output 2n phase shifted clock signals () at a third frequency and a multiplexer () connected to receive the 2n phase shifted clock signals from the divide by n clock divider () and output a third clock signal () selected by an input phase select signal ().

Radar system

The disclosure relates to monitoring of feedback systems such as phase lock loops. A system is disclosed, comprising: a feedback circuit (); and a monitoring module (). The monitoring module () is configured to: i) receive actual values of at least one state variable describing the state of the feedback circuit at a first time; ii) determine a predicted future value of the at least one state variable at a second time from the actual values at the first time using a model of the feedback circuit; iii) receive actual values of the at least one state variable at the second time; iv) compare the predicted future value of the at least one state variable at the second time with the actual value of the at least one state variable at the second time; and v) determine whether the feedback circuit has a fault condition, depending on the results of step iv).

Feedback system monitoring

The disclosure relates to apparatus and methods for self-testing of a duty cycle detector. Example embodiments include a circuit () comprising: a clock signal generator () configured to provide an output clock signal () having a duty cycle; a duty cycle detector () arranged to receive the output clock signal () and provide an output flag if the duty cycle of the clock signal () is outside a predetermined range; a controller () arranged to provide a duty cycle select signal () to the clock signal generator () to cause the clock signal () to have a duty cycle outside the predetermined range and to receive the output flag to confirm operation of the duty cycle detector ().

Duty cycle detector self-testing

A control system for a digitally controlled oscillator with temperature compensation including a loop detector providing an error value, filter circuitry providing a lower resolution digital value to the DCO to generate an output oscillation signal at a frequency within a lower resolution range, tracking circuitry holding a tracking digital value at a tracking offset from center of a tracking range while the lower resolution digital value is being determined, and then regulating the frequency within a higher resolution range by adjusting the tracking digital value, temperature compensation circuitry performing temperature compensation steps to maintain the tracking digital value between first and second thresholds within the predetermined tracking range, and a controller configured to set the first and second thresholds within a narrow range around the tracking offset during a standard operating mode, and to adjust one or both thresholds within a wide range during a critical operating mode.

System and method of controlling frequency of a digitally controlled oscillator with temperature compensation

A method for clock frequency monitoring for a Phase-Locked Loop (PLL) based design includes determining a present operating point of an oscillator of the PLL based design, wherein the oscillator generates a present frequency in response to the present operating point. The present operating point of the oscillator is compared to a comparison range defined by a plurality of reference operating points, wherein the oscillator generates a nominal reference frequency in response to a nominal one of the plurality of reference operating points and the comparison range is further defined by a manufacturing process range, an operating voltage range and an operating temperature range. An action is performed in response to the present operating point being outside of the comparison range.

Clock frequency monitoring for a phase-locked loop based design

A fractional-N all digital phase locked loop (ADPLL) includes a randomly modulated delay having a triangular distribution to a frequency reference at an input of the fractional-n ADPLL to reduce spurious tones introduced by delta-sigma modulation of a frequency control word without requiring active control or calibration. In some embodiments, a delay line generates the randomly modulated delay based on a uniformly distributed random number with a flat spectrum that is shaped by a high pass filter.

Fractional-N ADPLL with reference dithering

A built-in self-test (BIST) block is provided that is incorporated into an all-digital phase locked loop (ADPLL) located on chip with the ADPLL. The BIST performs testing functions without need for support external to the chip. Test setup, test control, and test evaluation are performed entirely on chip. The BIST provides information regarding success or failure of the testing and can provide error information regarding test cases that do not pass successfully.

Configurable built-in self-test for an all digital phase locked loop

A hardware device includes a frequency lock loop (FLL) that includes a phase loop filter, and a phase lock loop (PLL) such as an all digital PLL (ADPLL) that includes a frequency loop filter. A controller provides a first control signal to the FLL and a second control signal to the PLL when the device operates the same. The device can also include a digital controlled oscillator (DCO) and part of one or more of the FLL and the PLL. The FLL and the PLL include first and second filters, respectively. The filters are coupled to the DCO. A time-to-digital converter (TDC) and a divider receive an input from the DCO. The controller forms a first loop with the first filter, the TDC, and the divider, and the controller forms a second loop with the second filter, the TDC, and the divider.

All digital phase locked loop (ADPLL) with frequency locked loop

A method for Phase Locked Loop (PLL) lock detection includes determining a phase error by comparing a feedback phase to a reference phase. A frequency error is determined by comparing a feedback frequency to a reference frequency. A lock signal is determined in response to the phase error being less than an upper phase threshold and greater than a lower phase threshold, and the frequency error being less than an upper frequency threshold and greater than a lower frequency threshold.

Phase locked loop with phase and frequency lock detection

An apparatus includes signal control circuitry, a phase-locked loop (PLL), and a correlation circuit. The signal control circuitry provides a reference clock signal carrying pseudo-random phase noise and as derived from an application clock signal and pseudo-random noise. The PLL, responsive to the reference clock signal carrying the pseudo-random phase noise, provides an output signal that is related to the phase of the reference clock signal. The correlation circuit self-tests the PLL by cross-correlating a signal corresponding to the output signal from the phase detector with the pseudo-random noise and, in response, by assessing results of the cross-correlation relative to a known threshold indicative of a performance level of the PLL.

Self-testing of a phase-locked loop using a pseudo-random noise

An all digital phase locked loop system for tracking a variable frequency input signal and method of operation are described. The ADPLL system includes a digital phase locked loop, including a digitally controlled oscillator, and a model of the digitally controller oscillator. The model represents the behaviour of the digitally controlled oscillator as a function of frequency and has a model input arranged to receive a signal indicating a current target frequency. The model is configured to output at least one control signal to control the frequency of the digitally controlled oscillator to be closer to the current target frequency. The digital phase locked loop is configured to control the digitally controlled oscillator to reduce any difference between the frequency of the digitally controlled oscillator and the current target frequency arising from any deviation of the model of the digitally controlled oscillator from the digitally controlled oscillator.

Digital phase locked loops

A phase locked loop, comprising: a phase detector configured to determine a phase difference (&#x394;&#x3c6;) between a reference signal and a feedback signal; a loop filter configured to perform a filtering operation on a signal derived from the phase difference, and to provide a control signal; a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; wherein a low-pass filter is provided between the phase detector and the loop filter and/or between the loop filter and the frequency controlled oscillator to reduce quantization noise from the phase detector.

Phase locked loop with reduced noise

A phase locked loop is disclosed comprising: a phase detector, loop filter and a frequency controlled oscillator. The phase detector is configured to determine a phase difference between a reference signal and a feedback signal. The loop filter is configured to perform a filtering operation on a signal derived from the phase difference and to provide a control signal. The frequency controlled oscillator is configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal. The phase locked loop further comprises a lock detector, including: a phase lock detector configured to receive a first signal from the phase locked loop, and to derive a phase lock signal from the first signal; a frequency lock detector configured to receive a second signal from the phase locked loop, and to derive a frequency lock signal from the second signal. An unlock detector may be provided, configured to determine whether the first signal has changed by a predetermined amount during a predetermined period.

Phase locked loop with lock detector

Settling time may be reduced or eliminated for a phase-locked loop (ADPLL). An oscillator model provides proper settings that are applied to compensate both the frequency response and the phase response. A hardware device may include a Digital Controlled Oscillator (DCO); and a DCO model device with a processor, wherein the processor is configured to calculate a frequency for the DCO by searching for the frequency based upon operational parameters of the DCO, compare the calculated frequency to a measured frequency, and compensate, based upon the comparison, an ADPLL to decrease a settling time.

Growing community of inventors

Moisburg, Germany

Ulrich Moehlmann