Qimonda Ag

Altis Semiconductor, Snc

Infineon Technologies Ag

International Business Machines Corporation

Synopsys, Inc.

Altis Semiconductor

Infineon Technologies North America Corp.

Centre National De La Recherche Scientifique

Université Paris—sud

Atlis Semiconductor

Ulrich Karl Klostermann

Rainer Leuschner

Wolfgang Raberg

Franz Kreupl

Philip Louis Trouilloud

Manfred Ruehrig

Daniel Braun

Chanro Park

Peter Beer

Michael Kund

Dietmar Gogl

Joachim Wecker

Yudhishthir Prasad Kandel

Rok Dittrich

Ulrich Welling

Daniel Christopher Worledge

Richard Ferrant

Juergen Zimmer

Stuart Stephen Papworth Parkin

Lawrence S Melvin, Iii

Mahesh Govind Samant

Arunava Gupta

Klaus-Dieter Ufert

Ulrike Gruening-von Schwerin

Qiliang Yan

Ralf Symanczyk

Stephen L Brown

Gill Yong Lee

Kevin D Lucas

Bernhard Ruf

Petra Majewski

Hubert Brueckl

Dieter Andres

Hans-Jürgen Stock

Alexander Duch

Jacques Miltat

Yoshinobu Nakatani

Zachary Adam Levinson

Michael Vieth

Erik A Verduijn

Jiuzhou Tang

Christian Alof

Christian Ruester

Rainer Bruchhaus

Ulrike Grüning-von Schwerin

Human Park

A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.

Predicting defect rate based on lithographic model parameters

In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.

Stochastic-aware lithographic models for mask synthesis

Certain aspects relate to a method for improving a lithography configuration. In the lithography configuration, a source illuminates a mask to expose resist on a wafer. A processor determines a defect-based focus exposure window (FEW). The defect-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of defects on the wafer. The defect-based FEW is determined based on a predicted probability distribution for occurrence of defects on the wafer. A processor also determines a critical dimension (CD)-based FEW. The CD-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of CD variation on the wafer. It is determined based on predicted CDs on the wafer. The lithography configuration is modified based on increasing an area of overlap between the defect-based FEW and the CD-based FEW.

Lithography improvement based on defect probability distributions and critical dimension variations

An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.

Condensed memory cell structure using a FinFET

A method (and structure) of thermally treating a magnetic layer of a wafer, includes annealing, for a predetermined short duration, a magnetic layer of a single wafer.

Method and apparatus for fast and local anneal of anti-ferromagnetic (AF) exchange-biased magnetic stacks

A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Twhich is lower than the writing mode operating temperature of the magnetic random access memory structure. The artificial anti-ferromagnet is magnetically coupled to the anti-ferromagnet, and includes first and second magnetic layers, and a coupling layer interposed therebetween, the first and second magnetic layers having different Curie point temperatures. The barrier layer is positioned to be between the second magnetic layer and the free magnetic layer.

MRAM device structure employing thermally-assisted write operations and thermally-unassisted self-referencing operations

An integrated circuit includes an array of memory cells and a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of memory cells. The integrated circuit includes conductive cladding contacting the doped semiconductor line.

Integrated circuit including doped semiconductor line having conductive cladding

According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.

Integrated circuit

An integrated circuit having a magnetic tunnel junction and method. One embodiment provides an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction includes a barrier layer. The barrier layer includes carbon, pyrolytic carbon, or graphene, or graphite.

Integrated circuit having a magnetic tunnel junction device and method

According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.

Integrated circuit, memory cell array, memory module, and method of operating an integrated circuit

A magnetoresistive memory cell has a magnetic stack providing an effective anisotropy field of a storage layer of the magnetic stack during thermal select heating, at least one line providing at least one external magnetic field to the magnetic stack, the effective anisotropy field and the at least one external magnetic field having a non-zero angle relative to one another.

Magnetoresistive memory cell

An integrated circuit includes a plurality of magnetic tunneling junction stacks, each magnetic tunneling junction stack including a reference layer, a barrier layer and a free layer, wherein the plurality of magnetic tunneling junction stacks share a continuous common reference layer.

Integrated circuit, memory module, and method of manufacturing an integrated circuit

Magnetoresistive sensors with tunnel barrier and method. One embodiment provides a magnetoresistive sensor having a magnetic tunnel junction is provided. The magnetic tunnel junction includes a barrier layer. The barrier layer includes carbon, pyrolytic carbon, or graphene, or graphite.

Magnetoresistive sensor with tunnel barrier and method

According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered.

Integrated circuit, method of manufacturing an integrated circuit, and memory module

Growing community of inventors

Munich, Germany

Ulrich Karl Klostermann