Infineon Technologies Ag

Tenovis Gmbh & Co. Kg

Ulrich Glaser

Yiqun Cao

Andreas Peter Meiser

Franz Hirler

Kai Esmark

Michael Mayerhofer

Julien Lebon

Harald Gossner

Matthias Stecher

Joost Adriaan Willemen

Magnus-Maria Hell

Anton Mauder

Joachim Weyers

Andreas Rupp

Christian Lenzhofer

Hans-Joachim Schulze

Peter Irsigler

Martin Streibl

Adrian Finney

Herbert Gietler

Thorsten Hinderer

Andrei Cobzaru

Bogdan-Eugen Matei

Markus Mergens

Dragos Panaite

Gilles Guerrero

Nico-Johannes Maldener

A circuit for preventing failure of a device includes a first rail, electrostatic discharge (ESD) protection circuitry, a second rail, an ESD switching circuitry, biasing circuitry, and a signal limiter. The first rail is for one or more first electrical components formed in a first portion of a substrate. The second rail is for one or more second electrical components formed in a second portion of the substrate. The first portion of the substrate forms an emitter of a parasitic transistor and the second portion of the substrate forms a collector of the parasitic transistor. The biasing circuitry is configured to output a bias voltage at the emitter of the parasitic transistor when the ESD switching circuitry is switched on. The signal limiter electrically couples to the first rail and the emitter of the parasitic transistor.

Electrostatic discharge with parasitic compensation

A circuit includes electrostatic discharge (ESD) protection circuitry, triggering circuitry, transient detection circuitry, and deactivation circuitry. The ESD protection circuitry is coupled between a first rail and a second rail. The triggering circuitry is configured to generate an ESD activation signal when a voltage across the first rail and the second rail exceeds a voltage threshold. The ESD protection circuitry is configured to activate based on the ESD activation signal. The transient detection circuitry is configured to generate a deactivation signal when the voltage across the first rail and the second rail comprises a voltage change over time that is less than a transient threshold. The deactivation circuitry is configured to deactivate the triggering circuitry based on the deactivation signal.

Active ESD clamp deactivation

An electrostatic discharge clamp for groups of terminals having cascaded and different voltage classes, a plurality of discharge paths, and a multiple-input trigger circuit. In response to detecting a positive voltage event at any of the groups of terminals, the trigger circuitry can turn on an electronic switch causing current caused by the voltage event to flow through one or more of the discharge paths instead of through functional circuitry which could potentially be damaged by the current caused by the voltage event.

Central combined active ESD clamp

An integrated circuit having an ESD protection structure is described. One embodiment includes a circuit section interconnected with a first terminal and with a second terminal and being operable at voltage differences between the first terminal and second terminal of greater than +10 V and less than &#x2212;10 V. The integrated circuit additionally includes an ESD protection structure operable to protect the circuit section against electrostatic discharge between the first terminal and the second terminal. The ESD protection structure is operable with voltage differences between the first and second terminals of greater than +10 V and less than &#x2212;10 V without triggering. The ESD protection structure is electrically and optically coupled to a photon source such that photons emitted by the photon source upon ESD pulse loading are absorbable in the ESD protection structure and an avalanche breakdown is initiatable by electron-hole pairs generated by the absorbed photons.

Integrated circuit having an ESD protection structure and photon source

A semiconductor device includes a semiconductor body including a first trench extending into the semiconductor body from a first surface and a diode including an anode region and a cathode region. One of the anode region and the cathode region is at least partly arranged in the first trench. The other one of the anode region and the cathode region includes a first semiconductor region directly adjoining the one of the anode region and the cathode region from outside of the first trench, thereby constituting a pn junction. The semiconductor device further includes a conducting path through a sidewall of the first trench.

Semiconductor device including a diode at least partly arranged in a trench

An apparatus and a method for generating signals for ESD stress testing an electronic device are disclosed. In an embodiment the apparatus is configured to receive a source signal including a source pulse, delay the source pulse to generate a test signal including a test pulse with a pulse width in an ESD time range and generate an auxiliary signal including an auxiliary pulse with a pulse width in the ESD time range.

Apparatus and method for generating signals for ESD stress testing an electronic device and system for performing an ESD stress test of an electronic device

A method of triggering avalanche breakdown in a semiconductor device includes providing an electrical coupling and an optical coupling between an auxiliary semiconductor device configured to emit radiation and the semiconductor device including a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer. The electrical and optical coupling includes triggering emission of radiation by the auxiliary semiconductor device and triggering avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device.

Method of triggering avalanche breakdown in a semiconductor device

A circuit is described comprising electrostatic discharge (ESD) protection circuitry, keep-off circuitry and ESD detection circuitry. When the ESD detection circuitry detects an ESD event, the ESD detection circuitry is configured to both enable the ESD protection circuitry and disable the keep-off circuitry.

Noise-tolerant active clamp with ESD protection capability in power up mode

One embodiment of an integrated circuit includes a semiconductor body. In the semiconductor body a first trench region extends into the semiconductor body from a first surface. The integrated circuit further includes a diode including an anode region and a cathode region. One of the anode region and the cathode region is at least partly arranged in the first trench region. The other one of the anode region and the cathode region includes a first semiconductor region adjoining the one of the anode region and the cathode region from outside of the first trench region.

Semiconductor device including a diode arranged in a trench

A semiconductor device includes a trench extending into a semiconductor body from a first surface. At least one of a ternary carbide and a ternary nitride is in the trench.

Semiconductor device and manufacturing method

A semiconductor component includes an auxiliary semiconductor device configured to emit radiation. The semiconductor component further includes a semiconductor device. An electrical coupling and an optical coupling between the auxiliary semiconductor device and the semiconductor device are configured to trigger emission of radiation by the auxiliary semiconductor device and to trigger avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device. The semiconductor device includes a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer.

Semiconductor component and method of triggering avalanche breakdown

A combined electro static discharge clamp for cascaded voltage pins can include an electronic switch, a plurality of discharge paths, and a plurality of trigger circuits. In response to detecting a voltage event across any two voltage pins, the trigger circuitry can turn on the electronic switch causing current caused by the voltage event to flow through one or more of the discharge paths instead of through functional circuitry which could potentially be damaged by the current caused by the voltage event.

Combined ESD active clamp for cascaded voltage pins

A two-stage protection device for an electronic component protects against transient disturbances. The electronic component may be a semiconductor component, and may include one or multiple transistors and/or an integrated circuit. The protection device is connected to at least a first contact and a second contact of the electronic component, and is disposed essentially in parallel to the component that is to be protected, between the first contact and the second contact. The protection device includes a first stage with at least one diode and a second stage separated from the first stage by a resistor. The second stage includes at least one diode arrangement having two back-to-back disposed diodes which are disposed cathode-to-cathode.

ESD protection

A semiconductor device includes a first semiconductor element including a first pn junction between a first terminal and a second terminal. The semiconductor device further includes a semiconductor element including a second pn junction between a third terminal and a fourth terminal. The semiconductor element further includes a semiconductor body including the first semiconductor element and the second semiconductor element monolithically integrated. The first and third terminals are electrically coupled to a first device terminal. The second and fourth terminals are electrically coupled to a second device terminal. A temperature coefficient &#x3b1;of a breakdown voltage Vof the first pn junction and a temperature coefficient &#x3b1;of a breakdown voltage Vof the second pn junction have a same algebraic sign and satisfy 0.6&#xd7;&#x3b1;&#x3c;&#x3b1;&#x3c;1.1&#xd7;&#x3b1;at T=300 K, wherein V&#x3c;V.

Semiconductor device including first and second semiconductor elements

A protection circuit includes a controllable discharge element having a load path coupled between a first second circuit nodes. The discharge element provides a discharge path between the first and the second circuit nodes when in an on state. A trigger circuit has a first connection coupled to the first circuit node and a second connections coupled to the second circuit node. The trigger circuit is configured to produce a drive signal that switches the discharge element to its on state when the voltage between the first and the second circuit nodes reaches a trigger value. A setting circuit coupled to the trigger circuit is configured to change the trigger value from a first trigger value to a second trigger value depending on a voltage between the first and the second circuit nodes and/or on the drive signal.

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Putzbrunn, Germany

Ulrich Glaser