Infineon Technologies Ag

Ulrich Frey

Gunther Lehmann

Matthias Goldbach

Matthias Lehr

Dominique Savignac

Dirk Offenberg

Axel Brintzinger

J&uuml;rgen Lindolf

Jochen M&uuml;ller

Andreas Felber

Jürgen Lindolf

Björn Fischer

Stefan Dankowski

Kamel Ayadi

Oliver Weinfurtner

The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises the following steps: provision of a semiconductor substrate () with a gate dielectric (); provision of a plurality of multilayered, elongate gate stacks (GSGS) which essentially run parallel to one another on the gate dielectric (), which gate stacks have a bottommost layer () made of silicon; provision of a first liner layer () made of a first material over the gate stacks (GSGS) and the gate dielectric () uncovered beside the latter, the thickness (h) of which liner layer is less than a thickness (h') of the bottommost layer () made of silicon; provision of sidewall spacers () made of a second material on the vertical sidewalls of the gate stacks (GSGS) over the first liner layer (), a region of the first liner layer () over the gate dielectric () between the gate stacks (GSGS) remaining free; selective removal of the first liner layer () with respect to the sidewall spacers () for the purpose of laterally uncovering the bottommost layer () made of silicon of the gate stacks (GSGS); and selective oxidation of the uncovered bottommost layer () for the purpose of forming sidewall oxide regions (&#x2032;) on the gate stacks (GSGS).

Fabrication method for a semiconductor structure and corresponding semiconductor structure

Transistor structures, with one source/drain region connected to a charge storage device to be insulated includes an asymmetric gate conductor structure. At a first side wall, which faces the one source/drain region, the asymmetric gate conductor structure has a side wall oxide with a greater thickness and a bird's beak structure with a greater length than at an opposite, second side wall. An effective channel length is increased for the same feature size of the gate conductor structure. Memory cells can be realized in a higher density.

Transistor structure, memory cell, DRAM, and method for fabricating a transistor structure in a semiconductor substrate

An antifuse apparatus includes first and second independent current paths connected to an antifuse. One of the current paths can be used to program the antifuse, and the other current path can be used to detect the status (programmed or not programmed) of the antifuse.

Antifuse programming with relaxed upper current limit

The invention relates to a semiconductor circuit () having an electrically programmable switching element (), an 'antifuse', which includes a substrate electrode (), produced in a substrate () which can be electrically biased with a substrate potential (Vo), and an opposing electrode () which is isolated from the substrate electrode () by an insulating layer (), where the substrate electrode () includes at least one highly doped substrate region (), and where the opposing electrode () can be connected to an external first electrical potential (V+) which can be provided outside of the semiconductor circuit (). In line with the invention, the substrate electrode () can be connected to a second electrical potential (V&#x2212;), which is provided inside the circuit and which, together with the external first potential (V+), produces a higher programming voltage (V) than the external first potential (V&#x2212;) together with the substrate potential (Vo). In addition, the substrate electrode () is shielded from the substrate potential (Vo) by a current barrier layer (). This allows the second potential to be lowered below the substrate potential or to be raised above it; the resulting increased programming voltage does not endanger other circuit regions.

Integrated semiconductor circuit with an electrically programmable switching element

An anti-fuse system composed of a multiplicity of anti-fuse circuits ( N) connected across a voltage source ( ) by a pair of conductors ( ). Each anti-fuse circuit comprising an anti-fuse ( ) connected in a series with a blow or control transistor ( ) and a control circuit ( ) for monitoring the status of the anti-fuse ( ), Control circuit ( ) provides an &ldquo;on&rdquo; signal to the gate ( ) of control transistor ( ) only when a_&ldquo;select_&rdquo; signal is received at an input ( ) of control circuit ( ) and if anti-fuse ( ) has not been blown. After the anti-fuse ( ) is blown, control circuit ( ) turns off the control transistor ( ) thereby providing a constant power source voltage across each anti-fuse circuit ( N) regardless of the number of parallel anti-fuses which have been blown.

Self-terminating blow process of electrical anti-fuses

The present invention provides for evaluating a programmable anti-fuse element. For a programmable transistor anti-fuse, the gate of the anti-fuse is precharged with a predetermined voltage and/or current and the anti-fuse is subsequently evaluated. In one embodiment a precharge voltage sufficient to turn ON a transistor is provided to the gate. Here, an intact (unblown) transistor remains ON over a period of time and a damaged (blown) transistor dissipates the charge voltage and turns OFF. The status of the transistor is subsequently determined by evaluating the resistance between the drain and source. A high resistance indicates a blown condition and a low resistance indicates an unblown condition. In another embodiment, a small current is provided to the gate in which the small current is greater than a leakage current for an intact transistor and is less than a leakage current for a damaged transistor. An intact transistor charges to an ON state over a period of time but a damaged transistor does not because it's leakage current is greater than the small current provided to the gate. Again, the status of the transistor anti-fuse is subsequently determined by evaluating the resistance between the drain and source.

Evaluation circuit for an anti-fuse

The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate ( ); providing a metallization region ( ) comprising a first metal in the circuit substrate ( ); providing a first insulation layer ( ) above the metallization region ( ); forming an opening ( ) in the insulating layer ( ) in order to uncover at least part of the surface of the metallization region ( ); depositing a functional layer ( &prime;) above the resulting structure; depositing a second insulating layer ( ) above the resulting structure, in such a manner that the opening ( ) is filled; polishing-back of the second insulating layer ( ) and of the functional layer ( &prime;) in order to uncover the surface of the first insulating layer ( ); forming a contact ( &prime;) in the second insulating layer ( ) inside the opening ( ) in order to make contact with the functional layer ( &prime;); and providing an interconnect ( ) for electrical connection of the contact ( &prime;).

Growing community of inventors

Dresden, Germany

Ulrich Frey