Arm Limited

Mindspeed Technologies, Inc.

Ulrich Bortfeld

Karl G Andersson

Wade Guthrie

Don W Bebout

Debugging a multiprocessor system utilizing at least two debuggers is disclosed. A user command is issued through a first debugger to a first processor in the multiprocessor system. The user command can be converted to a debugger RPC command by a first proxy module associated with the first debugger. The user command can be intercepted by a scheduler. A second processor in the multiprocessor system is then informed, for example by the scheduler, of the issuance of the user command. The user command is executed by both the first and second processors and both the first and second debuggers can then be informed by means of processor RPC commands of the execution of the user command. The processor RPC commands can be converted to callback commands by respective first and second proxy modules associated with the first and second processors when being sent to the first and second debuggers.

Method and system for debugging multiprocessor systems

A method for accelerating hardware simulation is presented wherein cycle based simulations of digital system designs are generated by raising the level of abstraction in a hardware simulation environment. Behavioral models of the digital system components are created in a high level general purpose programming language. Function calls created in a high level general purpose programming language provide a transaction based communication interface. During a simulation of the system design, the behavioral models communicate with each other through the transaction based communication interface. Additionally, the behavioral models employ an execute and update method of instruction processing that generates cycle accurate information for the simulation.

Method and apparatus for accelerating hardware simulation

A significant improvement over current methods for co-simulation of the hardware and software components of embedded digital system designs is provided. The present invention integrates the hardware and software components of a system design into a single unified simulation environment. The unified simulation environment and the various component models of the system design are created in a high level general purpose programming language. This allows inter-component communications and communications with the unified simulation environment to be carried out through the use of function calls, which significantly increases the overall simulation speed. Additionally, the unified simulation environment runs as a single process, which significantly improves debugging capabilities. Furthermore, the present invention employs a higher level of abstraction than conventional simulation environments and thereby significantly increases simulation speed while moving away from the detail saturated event driven simulations of the past.

Method and apparatus for unified simulation

A debugging environment for a multi-processor simulator or emulator is disclosed. The simulator or emulator is ideally suited for the development of embedded software. The simulator can contain multiple processor models, with each processor model representing a processor. The simulator or emulator also includes a scheduler which controls the execution of the processor models. Each processor also communicates with a debugger via a debug adapter. The debug adapter acts as a pass-through filter for non-control commands which are communicated between a processor and its attached debugger. However, the debug adapter routes control commands to the scheduler. The scheduler ensures that all of the processors and debuggers maintain synchronization. Other modules can also be included in the multi-processor simulation environment, for example, clock gate modules.

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Irvine, CA, United States of America

Ulrich Bortfeld