International Business Machines Corporation

Cadence Design Systems, Inc.

Ulrich Baur

Franco Motika

Peilin Song

Richard Frank Rizzolo

William Vincent Huott

Otto Andreas Torreiter

David T Hui

Joseph E Eckelman

Mary Prilotski Kusko

Tobias Webel

Lawrence D Curley

Timothy J Koprowski

Ralf Ludewig

Ronald J Frishmuth

Kevin William McCauley

Ching Lung Tong

An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.

Integrated circuit arrangement for test inputs

LBIST and weighted LBIST tests are performed simultaneously on different portions of the tested object. This new test methodology and design change achieves the same test coverage and test time as the traditional test strategy with dramatic power reduction during test. It can be applied at wafer, chip, MCM, and system levels of test. Most importantly, it does not need new tools for support. Current test software will work as it does with the traditional test strategy. Scheduling the LBIST and weighted LBIST tests in the same test session reduces the overall power consumption because weighted LBIST testing consumes much less power than flat LBIST testing. In the same test session, if some parts of the logic is tested using weighted LBIST while the others were tested using LBIST, the power consumed by the circuit element at any given time is reduced.

VLSI chip test power reduction

The present invention relates to a test for current leakage of driver/receiver stages, and in particular for bi-directional input/output stages ( ) of a semiconductor chip. Two dedicated support transistor devices ( ) are added into the prior art switching scheme, together with a simple control logic ( ) for selectively controlling the two dedicated support transistor devices according to a predetermined test scheme. An on-chip self-test feature provides valid voltage levels which are convertible by the receiver ( ) to predictable logic states at the evaluation line RDATA. The test can be performed autonomously on the chip without the requirement for an external test device.

Self-test for leakage current of driver/receiver stages

For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated. When all the faults paths of the group falling below the threshold have been tested, a separate determined test generation program is activated. In the generated test, the fault is forced to propagate through the longest path above the threshold value.

Random path delay testing methodology

The present invention relates to a method and system for full parametric testing of the drive and receive capability of bi-directional driver/receiver-stages, and in particular of bi-directional input/output-stages of a semiconductor chip. Electrical properties, as for example DC-resistance, AC-impedance of a driver stage are tested by at least one test load implemented on the chip itself which causes a characteristic voltage drop usable for test evaluation. Advantageously, the output stage devices of P-type ( ) and N-type ( ), respectively, are split into at least two sub-devices P , P and N , N , and are controlled separately by a control logic ( ). Then, for example N is used for testing the P device, and P is used for testing the N-device. Thus, devices already present on the chip are re-used for test purposes, which makes off-chip testing unnecessary.

Self-test with split, asymmetric controlled driver output stage

The present invention, enables complementing the state of either the master (L ) or slave latch (L ) in the shift register latches (SRLs) without changing the state of the other. When this is done after properly loading the LSSD scan chain using a normal scan chain sequence, the next system clock sequence can be used to launch a desired transition from each SRL in the scan chain. The actual mechanism for complementing the state of latches in LSSD scan chains can vary depending on which one of the L or L latch is being complemented; details of the actual scan chain and Shift Register Latch (SRL) design; and the semiconductor chip circuit technology. The complementing function can be provided as an integral part of the SRL design with minimal impact to system path and performance. An alternate complementing method would be to use a self complementing latch function. In this design, the latch to be complemented does not require an additional input containing the complement value, but rather uses its current state as reference and switches to the opposite state. To accomplish this, a complement signal similar to a latch reset (i.e., reset-to-complement) can be used.

Global transition scan based AC method

A scan chain latch circuit is provided. The scan chain latch circuit includes a first shift register latch and a second shift register latch. The scan chain latch circuit also includes a multiplexor connected between the first and second shift register latches, the multiplexor has a select line for controlling the function of the multiplexor. The multiplexor is configured for implementing an inverting mode such that a logic value may be passed via the multiplexor from the first shift register latch to the second shift register latch in one of a non-inverted state and an inverted state based upon the state of the select line.

Growing community of inventors

Weil im Schoenbuch, Germany

Ulrich Baur