Avago Technologies International Sales Pte. Limited

Broadcom Corporation

Ullas Singh

Namik Kocaman

Arvindh Iyer

Kumar Thasari

Jun Cao

Afshin Momtaz

Bo Zhang

Delong Cui

Heng Zhang

Meisam Honarvar Nazari

Mohammadamin Torabi

Mehmet Batuhan Dayanik

Jaehun Jeong

Ali Nazemi

Adesh Garg

Anand Jitendra Vasani

Henry Arnold Park

Ramy Awad

Mahmoud Reza Ahmadi

Burak Catli

Mohammed Abdul-Latif

Saurabh Surana

Alberto Grassi

Amr Amin Hafez Amin Abou-El-Sonoun

A device includes a circuit that generates a first current associated with a voltage of a region of a semiconductor substrate, a second current associated with a temperature of the region, a third current associated with a first process parameter of the region, and a fourth current associated with a second process parameter of the region. A multiplexer of the device receives the first, second, third, and fourth currents and selects the currents one by one and periodically. A ring oscillator of the device is coupled to the multiplexer and receives the first, second, third, and fourth currents one by one and periodically, from the multiplexer. The ring oscillator oscillates at oscillation frequencies that are based on the received current from the multiplexer. The voltage, temperature, and the first and second process parameters of the region are determined based on the oscillation frequencies.

Ultra-compact and micropower circuit to monitor process, voltage, and temperature with high accuracy

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.

Successive approximation register analog to digital converter having adaptive current or voltage parameter adjustments

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

Successive approximation register analog to digital converter with reduced data path latency

Disclosed herein are related to a system and a method for high speed communication. In one aspect, the system includes a set of slicers configured to generate a slicer output signal digitally indicating a level of an input signal received by the set of slicers. The system includes a speculative tap coupled to the set of slicers, where the speculative tap is configured to select bits of the slicer output signal based on selected bits of a prior slicer output signal. The system includes a decoder coupled to the speculative tap, where the decoder is configured to decode the selected bits of the slicer output signal in a first digital representation into a second digital representation. The system includes a feedback generator coupled to the decoder, where the feedback generator is configured to generate a feedback signal according to the decoded bits of the slicer output signal.

High speed receiver

A keeper based switch driver can generate overlapping differential signals and increase a crossing point of the overlapping differential signals a first predetermined amount. Additionally, the keeper based switch driver can further increase the crossing point of the overlapping differential signals a second predetermined amount and limit signal swing to an absolute value of a drain-source voltage. A microprocessor can also be electrically connected to a DAC cell with keeper based switch driver through a performance detection circuit. The microprocessor can be configured to receive information from a performance detection circuit and control a current of a variable current source in a keeper bias circuit accordingly.

Apparatus and system for high speed keeper based switch driver

A low-power high-swing current-mode logic (CML) driver circuit includes a first differential-pair and a second differential-pair. The first differential-pair includes first transistors, and is coupled to a first voltage supply that supplies a first voltage. The second differential-pair includes second transistors, and a common node of the second differential-pair is coupled to a second voltage supply. The second voltage supply supplies a second voltage that is higher than the first voltage. Control terminals of the first transistors are coupled to control terminals of the second transistors to form input nodes of the driver circuit.

Low-power high swing CML driver with independent common-mode and swing control

An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.

Compact high-speed mixed-signal interface

Digitally controlled phase interpolator circuit. A phase selection control word undergoes decoding to generate a switch control word. The phase selection control word includes 2 quadrant indicating bits and phase interpolating bits for a 4 clock scheme (e.g., 4 clocks having phases 0&#xb0;, 90&#xb0;, 180&#xb0;, and 270&#xb0;). Such a phase selection control word could includes 3 sector indicating bits and phase interpolating bits for an 8 clock scheme (e.g., 8 clocks having phases 0&#xb0;, 45&#xb0;, 90&#xb0;, 135&#xb0;, 180&#xb0;, 225&#xb0;, 270&#xb0;, and 315&#xb0;). The gates of a number of differential pairs of transistors receive the various clock signals. A number of switching circuits direct current from corresponding current sources/supplies to coupled sources of the differential pairs of transistors, and an output clock is taken from coupled drains of the differential pairs of transistors. One or more current sources/supplies can be implemented to provide continuous current (e.g., in an always on manner) to the differential pairs of transistors.

Digitally controlled phase interpolator circuit

Growing community of inventors

Irvine, CA, United States of America

Ullas Singh