Infineon Technologies Ag

Uli Kretzschmar

Viola Rieger

Lin Li

The present disclosure provides a Peripheral Component Interconnect Express (PCIe) controller for a PCIe endpoint device. The PCIe controller includes: a PCIe link interface configured to receive an interrupt request message, wherein the interrupt request message is a message write transaction PCIe transport layer packet (TLP) including an address associated with the PCIe endpoint device and a data value including interrupt information; an interrupt request trigger register configured to receive the data value; a plurality of interrupt lines; and a decode logic circuit connected to the interrupt request trigger register and the plurality of interrupt lines, the decode logic circuit configured to automatically decode a plurality of data bits of the data value when received in the interrupt request trigger register and generate an interrupt signal and provide the interrupt signal on one of the plurality of interrupt lines to an interrupt handling circuit.

Devices, systems, and methods for PCIe endpoint interrupt

A message processing component may include an execution unit configurable to execute a set of tasks associated with one or more communication network messages. The set of tasks may include at least one of a message evaluation task or a cryptography task. The execution unit may be configured to provide functional safety in association with executing the set of tasks. The execution unit includes a set of time-multiplexed partitions. Each partition in the set of time-multiplexed partitions may be configurable to execute only one task included in the set of tasks. The message processing component may include an interface to one or more hardware accelerators available for use in association with the execution of the set of tasks. Only one partition, of the set of time-multiplexed partitions, may have access to the one or more hardware accelerators at a time.

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Munich, Germany

Uli Kretzschmar