Samsung Electronics Co., Ltd.

Uk-Rae Cho

Nam-Seog Kim

Tae-Hyoung Kim

Yong-Jin Yoon

Jong-Cheol Lee

Nam-seog Kim

Hak-soo Yu

Min-Su Kim

Jong-Mil Youn

Gun-Ok Jung

Sung-Ki Min

Chang-Won Kahng

Kwang-Jin Lee

Hyang-Ja Yang

Dae-Seong Lee

Su-Chul Kim

Chung-Hee Kim

Ji-Kyum Kim

Ji-Suk Kwon

Emil Kagramanyan

Young-Jae Son

Suk-Gi Choi

Sung-Hoon Kim

Jin-Ho Lee

Jung-Woo Park

Jae-Woo Seo

Su-Jin Park

Ju-Hyun Kang

Sang-shin Han

Kwon-il Sohn

Jeong-Suk Yang

Sukgi Choi

Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.

Semiconductor device and method for operating the same

Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first source electrode configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage source, a second source electrode configured to connect a second power rail to a second impurity region, the second power rail coupled to a second voltage source, the first and second voltage sources being different, a gate electrode on the first and second impurity regions, a first drain electrode on the first impurity region, a second drain electrode on the second impurity region and an interconnection line connected to the first drain electrode and the second drain electrode, the interconnection line forming at least one closed loop.

Semiconductor device and method of fabricating the same

A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.

Delay test device and system-on-chip having the same

A stacked memory cell for use in a high-density static random access memory is provided that includes first and second pull-down transistors formed in a first layer, a pass transistor connected between a gate of the second pull-down transistor and a bit line and formed in the first layer and a first and second pull-up transistors formed in a second layer located above the first layer and connected with the first and second pull-down transistors respectively to form an inverter latch. With the construction of a stacked memory cell having a lone pass transistor, cell size is reduced compared to a conventional six-transistor cell, and driving performance of the pass transistor can be improved.

Stacked memory cell for use in high-density CMOS SRAM

A delay-locked loop (DLL) circuit and a method for generating transmission core clock signals are provided, where the DLL circuit receives an applied external clock signal and generates a transmission core clock signal, the DLL circuit includes a delay circuit unit and a transmission core clock signal generating unit, the delay circuit unit delays the external clock signal through a plurality of delay units configured in a chain type and outputs a plurality of reference clock signals having different phases, the transmission core clock signal generating unit independently selects and controls two reference signals from the plurality of reference clock signals and thus independently generates transmission core clock signals by the number corresponding to &#xbd; times the number of reference clock signals, and the transmission core clock signals have different phases and a period equal to a period of the external clock signal, wherein transmission core clock signals having a precise phase difference are generated individually and independently.

Delay-locked loop circuits and method for generating transmission core clock signals

A data line layout structure comprises a plurality of first data lines, second data lines, a third data line, a first data line driver, and a second data line driver. The plurality of first data lines are connected to sub mats in a memory mat so that a predetermined number of first data lines are connected to each sub mat. The second data lines are disposed in a smaller quantity than the number of the first data lines so as to form a hierarchy with respect to the first data lines. The third data line is disposed to form a hierarchy with respect to the second data lines, and transfers data provided through the second data lines to a data latch. The first data line driver is connected between the first data lines and the second data lines, and performs a logical ORing operation for output of the first data lines so as to drive a corresponding second data line. The second data line driver is connected between the second data lines and the third data line, and performs a logical ORing operation for output of the second data lines so as to drive the third data line.

Data line layout and line driving method in semiconductor memory device

A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

Semiconductor memory device with hierarchical bit line structure

A phase interpolation circuit and method are provided that are capable of operating in a low voltage and capable of generating a substantially exact phase-interpolation signal, where the phase interpolation circuit is configured to output a phase interpolation signal having a phase between phases of at least two input signals and comprises an interpolation unit configured to discharge an output node by a first interpolation control signal in case a first input signal of two input signals having different phases is inputted to the interpolation unit when the output node has been precharged to a power supply voltage level, the interpolation unit additionally discharging the output node by a second interpolation control signal in case of input of a second input signal of the two input signals; a comparison unit for comparing a reference voltage level and a voltage level of the output node of the interpolation unit to output a signal corresponding to the comparison; and a short pulse generation unit for generating a short pulse in response to an output signal of the comparison unit.

Phase interpolation circuit and method of generating phase interpolation signal

An impedance control circuit includes an impedance detector, an output driver and an impedance controller. The impedance detector generates a first output value to a detection pad connected between an external determination resistor and a pull-up transistor array, and outputs a second output value to a resistance divider terminal commonly connected between a pull-up and pull-down transistor array in response to a pull-up control code data and a pull-down control code data. The output driver has a commonly connected pull-up and pull-down transistor array, and a compensating unit connected to the pull-up and pull-down transistor array of the output driver, to compensate for quantization error of the pull-up and pull-down control code data. The impedance controller performs a comparison and counting operation so that the first and second output values of the impedance detector become approximated to a predetermined reference value, and generates the pull-up and pull-down control code data.

Impedance control circuit in semiconductor device and impedance control method

In a layout structure of a plurality of metal oxide semiconductor (MOS) transistors, the layout structure may include a first group of MOS transistors having first drain regions and first source regions that are individually allocated to a group active region that is isolated from all sides by a trench isolation, and a second group of MOS transistors having second drain regions and second source regions allocated to the group active region. The second group is disposed between the first group and an edge of the group active region. One or both of the first drain regions and first source regions are not in contact with an edge of the trench isolation in a length direction of a finger-type gate electrode.

Layout structure of MOS transistors on an active region

Provided is an output impedance circuit, which has a constant output impedance regardless of a pad voltage, and an output buffer circuit including the output impedance circuit. The output impedance circuit includes an output stage and an impedance control stage. The output stage outputs a current corresponding to a DC bias voltage via an output terminal, and the impedance control stage controls the current flowing through the output stage in response to an output signal. The output stage includes a resistance component and a first MOS transistor. A first terminal of the resistance component is connected to the output terminal. A first terminal of the first MOS transistor is connected to a second terminal of the resistance component, a second terminal of the first MOS transistor is connected to a voltage source, and an input signal is input to a gate of the first MOS transistor.

Output impedance circuit and output buffer circuit including the same

Provided is a semiconductor memory device testable with a single data rate (SDR) or a dual data rate (DDR) pattern in a merged data input/output pin (DQ) test mode. The device includes a first path circuit, a second path circuit, and a merged output generator configured to generate a merged data bit having a SDR and/or DDR pattern.

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Suwon-si, South Korea

Uk-Rae Cho