Texas Instruments Corporation

Ujwal Radhakrishna

Yogesh Kumar Ramadass

Vinod Kuniganahalli Rai

Alexei Sadovnikov

Sheldon Douglas Haynie

Anant Shankar Kamath

Jeffrey Anthony Morroni

Kashyap Jayendra Barot

A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.

Semiconductor doped region with biased isolated members

A device includes first and second device terminals, a fuse, a first circuit, a first transistor, and a control circuit. The fuse terminal couples to the first device terminal. The first circuit couples to the second fuse terminal. The second fuse terminal has a first voltage. The first transistor has a first control input and first and second current terminals. The first current terminal couples to the second fuse terminal, and the second current terminal couples to the second device terminal. The control circuit: turns 'on' the first transistor into a saturation region if the first voltage exceeds a threshold and a current through the fuse exceeds a trip threshold current of the fuse; and turns “on” the first transistor into a linear region if the first voltage exceeds a threshold and a current through the fuse is below the trip threshold current of the fuse.

Fail-open isolator

A method comprises: forming a first metallization layer on a semiconductor die, the first metallization layer including a metal fuse; and forming a second metallization layer on the first metallization layer, in which the second metallization layer includes a thermal conductor spaced from the metal fuse, and the first metallization layer is between the second metallization layer and the semiconductor die.

Active metal fuses for DC-EOS and surge protection

An example integrated circuit includes: a substrate and a first metal fuse layer on the substrate, the first metal fuse layer having first and second electrical contacts, the first electrical contact adapted to be coupled to an input terminal, the second electrical contact adapted to be coupled to a diode. The example integrated circuit further includes a second metal fuse layer on the substrate, the second metal fuse layer having third and fourth electrical contacts, the third electrical contact coupled to the second electrical contact and adapted to be coupled to the diode, the fourth electrical contact coupled to a shunt circuit.

Methods and apparatus to improve performance of power path protection devices

An electronic device includes an input, an output, a metal fuse, a resistor, a heat control transistor, and a heat controller. The metal fuse is coupled between the input and the output. The resistor is coupled between the metal fuse and the heat control transistor. The heat control transistor is coupled between the resistor and a reference terminal of the electronic device, and the heat controller is configured to control a heater current of the heat control transistor.

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Sunnyvale, CA, United States of America

Ujwal Radhakrishna