Intel Corporation

Ujjwal Gupta

Ankush Varma

Nikhil Gupta

Yogesh Bansal

Nikethan Shivanand Baligar

Krishnakanth Venkata Sistla

Andrew J Herdrich

Vivek Garg

Dean A Mulla

Swadesh Choudhary

Jonathan M Eastep

Federico Ardanaz

Lakshmipriya Seshan

Nazar Syed Haider

Ripan Das

Adwait Purandare

Suresh Chemudupati

Eric Dehaemer

Aman Sewani

Asma Al-Rawi

Rupal Parikh

Nilanjan Palit

Pavithra Sampath

Stanley Chen

Ali Mohammad

Stephen Wang

Dorit Shapira

Shruthi Venugopal

Phani Kumar Kandula

Michael Tulanowski

Timothy Yee-Kwong Kam

Stephen Paul Haake

A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.

Performance level control in a data processing apparatus

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.

Workload aware power limiting and multiple-input multiple-output control

Growing community of inventors

Hillsboro, OR, United States of America

Ujjwal Gupta