Samsung Electronics Co., Ltd.

Uihui Kwon

Yonghee Park

Jaeho Kim

Daewon Ha

Kwanghee Lee

Myunggil Kang

Keunho Lee

Yongwoo Jeon

Seungkyu Kim

Hyoshin Ahn

Sangjun Yun

Youngseok Song

Seongnam Kim

Ahyoung Kim

Wook Su Lee

Jae Ho Kim

Sung-Dae Suk

JungChak Ahn

Yang Lu

Minwoong Seo

Munhyeon Kim

Krishna Bhuwalka

Sungchul Kim

Seoksan Kim

Sangwoo Pae

Takeshi Okagaki

Zhenhua Wu

Jaehyun Yoo

Jaehyok Ko

Kyuok Lee

Ken Machida

Weiyi Qi

JaeHoo Park

Yoonsuk Kim

Kanghyun Baek

Joohyung You

Junhyeok Kim

Udit Monga

Yeoil Yun

Euiyoung Song

Saetbyeol Ahn

Dawon Jeong

Jaehee Choi

Jongwook Jeon

An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.

Integrated circuit device

A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.

Semiconductor device

A semiconductor protection device includes: an N-type epitaxial layer, a device isolation layer disposed in the N-type epitaxial layer, an N-type drift region disposed below the device isolation layer, an N-type well disposed in the N-type drift region, first and second P-type drift regions, respectively disposed to be in contact with the device isolation layer, and spaced apart from the N-type drift region, first and second P-type doped regions, respectively disposed in the first and second P-type drift regions, first and second N-type floating wells, respectively disposed in the first and second P-type drift regions to be spaced apart from the first and second P-type doped regions, and disposed to be in contact with the device isolation layer, and first and second contact layer, respectively disposed to cover the first and second N-type floating well, to be in contact with the device isolation layer.

Semiconductor protection device

A method of estimating aging of an integrated circuit (IC) includes: obtaining a first process design kit (PDK) including a plurality of first device models corresponding to a plurality of devices provided by a process of fabricating the IC; obtaining values of aging parameters of device instances included in a netlist defining the IC, by performing a first circuit simulation based on the netlist and the first PDK; and obtaining aging data of the IC by performing a second circuit simulation based on the values of the aging parameters and the netlist, wherein each of the plurality of first device models includes at least one measurement command to be executed in the first circuit simulation to calculate an aging parameter.

Method and apparatus for estimating aging of integrated circuit

Provided are metal oxide field-effect transistor (MOSFET) devices having a metal gate structure, in which a work function of the metal gate structure is uniform along a length direction of a channel, and manufacturing methods thereof. The MOSFET devices include a semiconductor substrate, an active area on the semiconductor substrate and extending in a first direction, and a gate structure on the semiconductor substrate. The gate structure extends across the active area in a second direction that traverses the first direction and comprises a high-k layer, a first metal layer, a work function control (WFC) layer, and a second metal layer, which are sequentially stacked on the active area. A lower surface of the WFC layer may be longer than a first interface between a lower surface of the first metal layer and an upper surface of the high-k layer in the first direction.

Metal oxide semiconductor field-effect transistor (MOSFET) devices and manufacturing methods thereof

A method of guiding a semiconductor manufacturing process includes receiving semiconductor manufacturing process data corresponding to a target semiconductor product, generating first semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a technology computer-aided design (TCAD) model trained through machine learning based on training data including TCAD simulation data, generating second semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a compact model generated based on information of measurement of at least one semiconductor characteristic of a first semiconductor product, generating, based on the first semiconductor characteristic data and the second semiconductor characteristic data, a plurality of process policies respectively corresponding to a plurality of strategic references, by using a plurality of strategy models; and providing a final process policy corresponding to the target semiconductor product based on the plurality of process policies.

Method and electronic device for guiding semiconductor manufacturing process

An image sensor may include a semiconductor substrate having a light receiving surface thereon and a plurality of spaced-apart semiconductor photoelectric conversion regions at adjacent locations therein. A grating structure is provided on the light receiving surface. This grating structure extends opposite each of the plurality of spaced-apart photoelectric conversion regions. An optically-transparent layer is provided on the grating structure. This grating structure includes a plurality of spaced-apart grating patterns, which can have the same height and the same width. In addition, the grating patterns may be spaced apart from each other by a uniform distance. The grating structure is configured to selectively produce &#xb1;1 or higher order diffraction lights to the photoelectric conversion regions, in response to light incident thereon.

Image sensors having grating structures therein that provide enhanced diffraction of incident light

An image sensor comprising a substrate including an upper surface and a lower surface opposite each other and extending in a first direction and a second direction, a first isolation region in the substrate and apart from the upper surface in a third direction perpendicular to the first direction and second direction, the first isolation region defining a boundary of a photoelectric conversion region, a second isolation region in the substrate and extending in the third direction from the lower surface to the first isolation region, a plurality of transistors on the upper surface in the photoelectric conversion region, and a photoelectric conversion device in the substrate in the photoelectric conversion region. The first isolation region includes a potential well doped with an impurity of a first conductivity type, and the second isolation region includes an insulating material layer.

Image sensor

A standard cell design system is provided. The standard cell design system includes at least one processor configured to implement: a control engine that determines planar parameters and vertical parameters of a target standard cell, a three-dimensional structure generating engine that generates a three-dimensional structure of the target standard cell based on the planar parameters and the vertical parameters, an extraction engine that extracts a standard cell model of the target standard cell from the three-dimensional structure, an assessment engine that performs a plurality of assessment operations based on the standard cell model, and an auto-optimizing engine that adjusts, based on a machine learning algorithm, the planar parameters and the vertical parameters based on results of the plurality of assessment operations.

Standard cell design system, standard cell design optimization method thereof, and semiconductor design system

A method of designing a semiconductor circuit using a circuit simulation tool executed by a computer includes calculating power consumptions of elements of the semiconductor circuit by use of the circuit simulation tool. A thermal netlist is created about the semiconductor circuit, based on the power consumptions and geometry information of each of the elements. A simulation of the semiconductor circuit is performed with the thermal netlist using the circuit simulation tool to detect a temperature of each of the elements. The thermal netlist includes thermal capacitance information of each of the elements.

Simulation system estimating self-heating characteristic of circuit and design method thereof

Provided is a finFET device. The finFET device may include an active region which protrudes vertically from a substrate, a channel region disposed on a center of the active region, a drain region disposed on one side surface of the channel region, and a source region disposed on the other side surface of the channel region, a gate insulating layer formed on two opposing side surfaces of the channel region and having a U-shaped cross-section, gate spacers formed on outer surfaces of the gate insulating layer, drain spacers formed on two opposing side surfaces of the drain region, and source spacers formed on two opposing side surfaces of the source region, and at least one of the two side surfaces of the drain region has a tapered part.

Semiconductor devices having tapered active regions

Provided are a semiconductor device and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an active fin on a substrate; oxidizing a portion of the active fin to form an insulating pattern between the active fin and the substrate; forming a first gate pattern on the substrate, wherein the first gate pattern crosses the active fin; exposing the substrate on both sides of the first gate pattern; and forming source/drain regions on the exposed substrate.

FinFET semiconductor device and method of manufacturing the same

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Hwaseong-si, South Korea

Uihui Kwon