Samsung Electronics Co., Ltd.

Ueno Tetsuji

Hwa-Sung Rhee

Dong-Suk Shin

Seung-Hwan Lee

Ho Joong Lee

Ho Young Lee

Seung-hwan Lee

Hyun-Suk Kim

Moon-han Park

Jae-Yoon Yoo

An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.

Method of forming an at least penta-sided-channel type of FinFET transistor

Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.

Semiconductor devices having faceted channels and methods of fabricating such devices

At least penta-sided-channel type of FinFET transistor

In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.

Method of fabricating CMOS transistor and CMOS transistor fabricated thereby

According to some embodiments of the invention, there is provided line photo masks that includes transistors having reinforcement layer patterns and methods of forming the same. The transistors and the methods provide a way of compensating a partially removed amount of a strained silicon layer during semiconductor fabrication processes. To the end, at least one gate pattern is disposed on an active region of a semiconductor substrate. Reinforcement layer patterns are formed to extend respectively from sidewalls of the gate pattern and disposed on a main surface of the semiconductor substrate. Each reinforcement layer pattern partially exposes each sidewall of the gate pattern. Impurity regions are disposed in the reinforcement layer patterns and the active region of the semiconductor substrate and overlap the gate pattern. Spacer patterns are disposed on the reinforcement layer patterns and partially cover the sidewalls of the gate pattern.

Transistors having reinforcement layer patterns and methods of forming the same

Growing community of inventors

Suwon-si, South Korea

Ueno Tetsuji