Intel Corporation

Udo Walterscheidt

Sailesh Kottapalli

Thomas Y Yeh

Andrew Y Sun

Kinkee Sit

Bharadwaj Pudipeddi

Kevin W Rudd

Saliesh Kottapalli

A system and method for determine which threads to execute at a given time in a multi-threaded computer system. A thread prioritizer determines execution fairness between pairs of potentially executing threads. A switch enabler determines forward progress of each executing thread. The resulting indicators from the thread prioritizer and switch enabler may aid in the determination of whether or not to switch a particular potentially executing thread into execution resources.

Method and apparatus for ensuring fairness and forward progress when executing multiple threads of execution

A method and apparatus for converting memory instructions to prefetch operations during a thread switch window is disclosed. In one embodiment, memory access instructions that are already inside an instruction pipeline when the current thread is switched out may be decoded and then converted to the complementary prefetch operations. The prefetch operation may place the data into the cache during the execution of the alternate thread.

Method and apparatus for converting memory instructions to prefetch operations during a thread switch window

In a multi-threaded processor, a long latency data dependent thread is flushed from the execution pipelines. Once the stalled thread is flushed, the non-stalling threads in the pipeline can continue their execution. Several resources are used to reduce this unwanted impact of stalls on the non-stalling threads. Also, these resources ensure that the earlier stalled thread, now flushed, is re-executed when the data dependency is resolved.

Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor

A method and apparatus for improving dispersal performance of instruction threads is described. In one embodiment, the dispersal logic determines whether the instructions supplied to it include any NOP instructions. When a NOP instruction is detected, the dispersal logic places the NOP into a no-op port for execution. All other instructions are distributed to the proper execution pipes in a normal manner. Because the NOP instructions do not use the execution resources of other instructions, all instruction threads can be executed in one cycle.

Method and apparatus for improving dispersal performance in a processor through the use of no-op ports

A resource management system and method is disclosed. The resource management system and method enable first and second instructions, each of which requires access to a memory resource, to be processed in an instruction pipeline at the same time. The resource management system and method manage the memory resource to prevent a data hazard based on an order of receipt of a first instruction response and a second instruction response.

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San Jose, CA, United States of America

Udo Walterscheidt