Siemens Aktiengesellschaft

Infineon Technologies Ag

Udo Schwalke

Martin Kerber

Christoph Zeller

Wilfried Haensch

Heinrich Zeininger

Wilfried Hansch

Heinz Zeininger

Uwe Doebler

Michael Sebald

Markus Biebl

Michael Stoisiek

Herbert Schaefer

Burkhard Ludwig

Ulrich Scheler

Hellmut Joswig

Fritz Bieringer

Dirk Schumann

Heinrich J Zeininger

Ralf Burmester

A doped region is provided on a substrate. A plane with conductive useful structures and a conductive filler structure is arranged at the surface of the substrate. The conductive filler structure is conductively connected to the doped region. In this way, charging of the conductive filler structure, which is provided for improving the planarity of the circuit arrangement and has no circuit-oriented function, is avoided.

Integrated circuit arrangement and method for the manufacture thereof

In the manufacture of CMOS devices, the n&plus; gate is partially counterdoped with boron to produce a modified p-type FET that has improved short channel effects, reduced gate induced drain leakage and gate oxide fields for improved reliability. A doped polysilicon layer is formed over a silicon or silicon oxide substrate, and is counterdoped with boron to a level of about 1&times;10 /cm to 5&times;10 /cm to adjust the work function but without changing the essentially n-type character of the gate electrode. This single counterdoping step achieves improved results for sub-micron devices below 0.5 micron at low cost. For CMOS device manufacturing, the alternating n-type and p-type devices are made in similar manner but reversing the n-type and p-type dopants.

MOSFETs with improved short channel effects and method of making the same

The MOS transistor has field plates and a subarea of the gate formed from the same polysilicon layer. A gate oxide lying underneath them is produced at the beginning of the fabrication process and it therefore exhibits particularly high quality. The polysilicon in the active area is raised to the same level as the adjoining field oxide areas, resulting in a planar topology.

Semiconductor structure for a MOS transistor

In a method for manufacturing an integrated circuit arrangement, trenches that define active zones are formed in a substrate. A first insulating layer that fills the narrow trenches is conformally deposited and is structured with a mask and anisotropic etching such that spacers arise at sidewalls of the wide trenches and supporting locations arise in a region of the wide trenches. The surface of the active zones is uncovered by forming a second insulating layer with an essentially planar surface and by a planarizing layer erosion on the basis of chemical-mechanical polishing or conventional dry etching.

Method for manufacturing an integrated circuit arrangement

Process for producing an integrated circuit device with at least one MOS

Method of producing an MOS transistor

A circuit structure having at least one MOS transistor whose source/drain regions are doped by a first conductivity type and whose gate electrode is doped by a conductivity type which is opposite to the first. The gate electrode has a lower dopant concentration at at least one of its edges than in its center. In the ON state, the gate electrode is driven to accumulation, with the result being that no gate depletion occurs. Such a circuit structure is also suitable for CMOS circuits containing PMOS transistors having an n-doped gate.

Circuit structure having at least one MOS transistor and method for its

In the manufacture of CMOS devices, the n+ gate is partially counterdoped with boron to produce a modified p-type FET that has improved short channel effects, reduced gate induced drain leakage and gate oxide fields for improved reliability. A doped polysilicon layer is formed over a silicon or silicon oxide substrate, and is counterdoped with boron to a level of about 1.times.10.sup.13 /cm.sup.2 to 5.times.10.sup.16 /cm.sup.2 to adjust the work function but without changing the essentially n-type character of the gate electrode. This single counterdoping step achieves improved results for sub-micron devices at low cost. For CMOS device manufacturing, the alternating n-type and p-type devices are made in similar manner but reversing the n-type and p-type dopants.

MOSFETs with improved short channel effects

In producing a CMOS circuit, an n-channel MOS transistor and a p-channel MOS transistor are formed in a semiconductor substrate. In situ p-doped, monocrystalline silicon structures are formed by epitaxial growth selectively with respect to insulating material and with respect to n-doped silicon, such silicon structures being suitable as a diffusion source for forming source/drain regions of the p-channel MOS transistor. The source/drain regions of the n-channel MOS transistor are produced beforehand by means of implantation or diffusion. Owing to the selectivity of the epitaxy that is used, it is not necessary to cover the n-doped source/drain regions of the n-channel MOS transistor during the production of the p-channel MOS transistor.

Method for producing a CMOS circuit

Process for manufacturing an integrated CMOS circuit

In order to produce an integrated CMOS circuit, a dielectric layer and a silicon layer are applied to a substrate. During the formation of insulation structurers which insulate neighboring active regions in the substrate, the silicon layer is structured in such a way that it has separate sub-regions which are subsequently doped differently. By full-surface deposition of an electrically conductive layer and common structuring of the electrically conductive layer and the structured silicon layer differently doped gate electrodes and a metallization plane, by which the gate electrodes are electrically connected, are formed. Division of the silicon layer before doping prevents lateral dopant diffusion.

Process for the production of an integrated CMOS circuit

Shallow junction field effect transistors are made by a low temperature process comprising ion implanting source/drain regions through a buffer layer in two steps, the first an ion implant at high dosage and low energy and the second an ion implant at low dosage and high energy. Ion implantation through the buffer layer avoids crystallographic damage to the silicon substrate. By grading the sidewall spacers of the gate electrode, more or fewer ions can be implanted through the spacer foot to ensure continuity between the source/drain regions and the channel region under the gate electrode.

Low junction leakage mosfets with particular sidewall spacer structure

Semiconductor structure for an MOS transistor and method for fabricating

Deep submicran mosfets with defect enhanced CoSi2 formation and improved silicided junctions. A silicon wafer having a diffusion window is first precleaned with hydrofluoric acid. After the HF precleaning, the silicon wafer is transferred to a conventional cobalt sputtering tool where it is sputter cleaned by bombardment with low energy Ar+ions so as to form an ultra-shallow damage region. After the sputter cleaning, and without removing the wafer from the sputtering tool, Cobalt metal is deposited on the silicon wafer at room temperature and a CoSi2 layer is formed in the diffusion window.

Growing community of inventors

Heldenstein, Germany

Udo Schwalke