The United States of America As Represented by the Administrator of the

California Institute of Technology

Udo Lieneweg

Joseph Maserjian

Martin G Buehler

Brent R Blaes

Margaret A Frerking

A particle sensor array which in a preferred embodiment comprises a static random access memory having a plurality of ion-sensitive memory cells, each such cell comprising at least one pull-down field effect transistor having a sensitive drain surface area (such as by bloating) and at least one pull-up field effect transistor having a source connected to an offset voltage. The sensitive drain surface area and the offset voltage are selected for memory cell upset by incident ions such as alpha-particles. The static random access memory of the present invention provides a means for selectively biasing the memory cells into the same state in which each of the sensitive drain surface areas is reverse biased and then selectively reducing the reversed bias on these sensitive drain surface areas for increasing the upset sensitivity of the cells to ions. The resulting selectively sensitive memory cells can be used in a number of applications. By way of example, the present invention can be used for measuring the linear energy transfer of ion particles, as well as a device for assessing the resistance of CMOS latches to Cosmic Ray induced single event upsets. The sensor of the present invention can also be used to determine the uniformity of an ion beam.

Particle sensor array

A planar frequency tripler comprised of two semiconductor diode structures connected back-to-back by an n.sup.+ doped layer (N.sup.+) of semiconductor material utilizes an n doped semiconductor material for a drift region (N) over the back contact layer in order to overcome a space charge limitation in the drift region. A barrier layer (B) is grown over the drift region, after a sheet of n-type doping (N.sub.sheet) which forms a positive charge over the drift region, N, to internally bias the diode structure. Two metal contacts are deposited over the barrier layer, B, with a gap between them. To increase the power output of the diodes of a given size, stacked diodes may be provided by alternating barrier layers and drift region layers, starting with a barrier layer and providing a positive charge sheet at the interface of a barrier on both sides of each drift region layer with n-type .delta. doping. The stacked diodes may be isolated by etching or ion implantation to the back contact layer N.sup.+ and a separate metal contact deposited on each stacked diode.

Planar varactor frequency multiplier devices with blocking barrier

A system is provided for use with wafers that include multiple integrated circuits that include two conductive layers in contact at multiple interfaces. Contact chains are formed beside the integrated circuits, each contact chain formed of the same two layers as the circuits, in the form of conductive segments alternating between the upper and lower layers and with the ends of the segments connected in series through interfaces. A current source passes a current through the series-connected segments, by way of a pair of current tabs connected to opposite ends of the series of segments. While the current flows, voltage measurements are taken between each of a plurality of pairs of voltage tabs, the two tabs of each pair connected to opposite ends of an interface that lies along the series-connected segments. A plot of interface conductances on a normal probability chart, enables prediction of the yield of good integrated circuits from the wafer.

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Altadena, CA, United States of America

Udo Lieneweg