Infineon Technologies Ag

Udo Hartmann

Jochen Kallscheuer

Patric Stracke

Peter Beer

Gunnar H Krause

Sascha Nerger

Thierry Canaud

A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test results or the status of the test modes are output from the chip. The method includes providing a chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another. A first serial bit string is stored, the bit sequence of which can be assigned to at least one test mode, in the first register set. A bit sequence is transmitted for application of the logical combination between the first register set and the second register set to the first bit string stored in the first register set. The test results are read out by means of a serial second bit string.

Method for testing semiconductor chips by means of bit masks

An integrated memory includes a circuit for testing the operation of the memory, a register circuit is used for storing a bit combination, compression unit, to receive test data which have been read from the memory cells, and a memory unit to store a plurality of bits from a compressed bit fail map. Each of the bits is associated with a different address region. One of the bits registers an error data item within the associated address region. In addition, a decoder circuit is provided for receiving the compressed address and for accessing that bit in the memory unit, which is associated with a respective address region on the basis of the compressed address. A short evaluation time for a function test on the memory and flexible alignment with the individual memory size are made possible.

Integrated memory having a circuit for testing the operation of the integrated memory, and method for operating the integrated memory

A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers; programming the m different register groups by filling them with m first bit strings, each bit string being respectively assignable to a state of n test modes; transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and using a serial second bit string to read out test results or the status of the test modes.

Method for testing semiconductor chips using register sets

A semiconductor component and method of testing a semiconductor component is disclosed. The invention relates to the parallel testing of semiconductor memory components having a fully functional memory area, which are classified as all good memory, and of semiconductor memory components having a restricted memory area, which are classified as partial good memory. For testing semiconductor memory components classified as partial good memory, the result, independently of the result of the comparison for those test addresses which are assigned to a memory area outside the functional memory area of the semiconductor memory component classified as partial good memory, is overwritten with an error free signal and a semiconductor memory component classified as all good memory is simulated. The testing of semiconductor memory components classified as partial good memory is accelerated and simplified.

Semiconductor memory component and method for testing semiconductor memory components

A semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories is disclosed. In one embodiment, in order to test the semiconductor memory components, test data are written to the memory cell array and, in parallel therewith, to a test write register. The data written to the memory cell array are compared bit by bit with the data stored in the test write register. An error free signal is generated in the case of matching. For semiconductor memory components classified as partial good memory, the result, independently of the result of the comparison for those data lines which are assigned to a memory area outside the functional memory area of the semiconductor memory component classified as partial good memory, is overwritten with an error free signal and a semiconductor memory component classified as all good memory is simulated. The testing of semiconductor memory components classified as partial good memory is accelerated and simplified.

Semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories)

To trim interface devices on semiconductor devices, such as trimmable output drivers and terminations, a measurement current produced in the test apparatus is impressed onto the interface device, and a measurement voltage produced by the measurement current in the interface device is detected by a trimming unit provided within the semiconductor device and is trimmed using control elements and trimming registers controlled by the trimming unit. To this end, the trimming unit ascertains trimming information which is stored in nonvolatile fashion in a memory unit in the semiconductor device and is loaded into the trimming registers in the semiconductor device whenever the semiconductor device is started up.

Method and apparatus for internally trimming output drivers and terminations in semiconductor devices

The invention relates to a test arrangement for testing semiconductor circuit chips, in which a test signal received via a primary test channel from a driver amplifier of an item of test equipment is distributed via parallel sub-channels to a plurality of inputs of one or more semiconductor circuit chips under test the test arrangement having signal buffering circuits arranged in each sub-channel that receive and buffer the test signal from the driver amplifier before feeding it to the inputs of the semiconductor circuit chip(s).

Test arrangement for testing semiconductor circuit chips

A data memory to be tested is connected to a processing unit. Data items to be stored are produced from a test pattern data item in the processing unit and are stored in the data memory. The data memory is tested in that the test pattern data items are received from a test device, processed using a first function to form data items to be stored, and the data items are then stored. After the stored data items are read from the memory they are processed with a second function to form test data items whose number is once more smaller than the stored data items that are read from the memory.

Circuit and method for testing a data memory

An apparatus for the parallel and independent testing of a plurality of semiconductor devices disposed on a wafer, in which the semiconductor devices are in each case connected to a common voltage supply unit through a controllable isolating apparatus, a voltage-regulating unit, and a current-limiting unit, and to a method for operating such an apparatus.

Apparatus and method for the parallel and independent testing of voltage-supplied semiconductor devices

A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is set, the test mode is executed in the chip and test results are output from the chip. It is provided that, after the setting and before the performance of the test mode, a check mode is executed in which the status of the test mode set in the chip is read out in a defined format.

Method for testing semiconductor chips

A current measuring device in the form of a Hall sensor device is disposed in an individual current/voltage supply line device with a common current/voltage supply unit for providing a particularly flexible configuration for testing a plurality of semiconductor devices for which the individual current consumption is to be measured during testing individually for each semiconductor device.

Configuration for testing semiconductor devices

A test system for conducting a function test of a semiconductor element on a wafer and a method for conducting the test includes a voltage source providing a supply voltage of the element being tested, two supply contact pins connected to the voltage source for applying the supply voltage to terminal pads of the element being tested, a read contact pin producing a currentless electrical read connection of the test system to a terminal pad of the element being tested, and a means for regulating the output voltage delivered by the voltage source based upon the electrical potential of the read contact pin. As such, the supply voltage of the semiconductor element can be adjusted more precisely in the function test.

Test system for conducting a function test of a semiconductor element on a wafer, and operating method

An apparatus for calibrating the pulse duration of an output signal of a signal source may be used, in particular, for measuring and setting a duty cycle of a signal output from the signal source. The apparatus includes a comparator having a first input, a second input and an output. A reference voltage supply is provided, which is connected to the first input of the comparator. A charge storing capacitor, the charge state of which is adjustable as a function of the pulse duration of the output signal of the signal source, is connected to the second input of the comparator. Finally, the apparatus includes a processor for setting the pulse duration as a function of the comparison signal output at the output of the comparator. The apparatus for signal calibration allows an on-chip calibration and renders complicated external calibration systems superfluous.

Device and method for calibrating the pulse duration of a signal source

An apparatus for testing wafer-level semiconductor devices, in particular memory chips in which a tunable light source radiates energy onto the semiconductor devices. The tunable light source is constructed to adjust the radiated light to a specific wavelength and to a specific intensity and to project the light for a predetermined time. When the semiconductor devices are irradiated with the light, electrons in defective ones of the semiconductor devices, in which a distance between a valence band and a conduction band has a lower value as compared with that of defect-free ones of the semiconductor devices, can be transferred into the conduction band from the valence band. These defective or &ldquo;poor&rdquo; semiconductor devices can thus be separated out.

Apparatus for testing semiconductor devices

An integrated semiconductor memory includes memory cells in a plurality of memory cell arrays disposed on a semiconductor chip in levels running above one another. A plurality of the memory cells are respectively combined to form normal units of memory cells, as well as redundant units of memory cells for replacing a respective one of the normal units. The normal units and the redundant units respectively include memory cells from memory cell arrays in a plurality of the levels. In the case of a faulty memory cell, the relevant normal unit is replaced by one of the redundant units. This permits a reduced number of programmable elements to be used for programming the redundant memory cells to repair the memory. A method for repairing such a memory is also provided.

Growing community of inventors

Neuried, Germany

Udo Hartmann