Marvell International Limited

Marvell Israel (misl) Ltd.

Udi Shtalrid

Uri Erlich

Apparatus includes a plurality of ports and arbitration circuitry. The plurality of ports is configured to connect a memory to a respective plurality of processing units that are configured to access the memory. The arbitration circuitry is configured to grant the processing units access to the memory via the ports in accordance with an arbitration scheme including multiple, alternating priority periods, such that in each priority period a respective processing unit is assigned an absolute priority over others of the processing units and the others of the processing units are assigned predefined relative priorities over one another.

Dynamic arbitration schemes for multi-master memory systems

A turbo decoder has at least two Bahl, Cocke, Jelinek, and Raviv (BCJR) processors in parallel, each in serial communication with respective interleavers. The BCJR processors and interleavers are in communication with a memory module that is internally split into non-overlapping memory banks. The turbo decoder includes respective sorter circuits in communication with the output of each BCJR processor/interleaver. A sorter circuit receives a data block from a BCJR processor/interleaver and directs the data block to the memory bank designated by an address assigned to the data block by an interleaver.

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Moshav Nir Israel, Israel

Udi Shtalrid