Applied Materials, Inc.

Indian Institute of Technology Bombay

Udayan Ganguly

Christopher Sean Olsen

Johanes F Swenberg

Theresa Kramer Guarini

Yoshitaka Yokota

Tze Wing Poon

Wei Liu

Matthew S Rogers

Shiyu Sun

Jacob Newman

Malcolm J Bevan

Jing Tang

Johanes S Swenberg

Yonah Cho

Sunderraj Thirupapuliyur

Lucien Date

Vicky U Nguyen

Sean M Seutter

Swaminathan T Srinivasan

David Chu

Vivek Saraswat

Swaminathar Srinivasan

Pankaj Subhash Kumbhare

Yoshita Yokota

Johanes Swenburg

Sandip Gangadharrao Lashkare

Accordingly the embodiments herein provide a method for fabricating a neuron oscillator (). The neuron oscillator () includes a thermal insulating device connected with a resistor and a capacitor in series to produce self-sustained oscillations, where the resistor and the capacitor are arranged in parallel manner. The neuron oscillator () eliminates a requirement of an additional compensation circuitry for a consistent performance over a time under heating issues. Additionally, an ON/OFF ratio of the neuron oscillator () improves to a broader resistor range. Further, a presence of tunable synaptic memristor functionality of the neuron oscillator () provides a reduced fabrication complexity to a large scale ONN. An input voltage required for the neuron oscillator () is low (2-3 V) which makes it suitable to use with existing circuitries without using any additional converters. Additionally, an amplitude of the oscillations is a significant fraction of an applied bias which eliminates a need for an amplification.

Method for fabricating neuron oscillator including thermal insulating device

Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof

A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.

Multi-layer charge trap silicon nitride/oxynitride layer engineering with interface region control

Methods and apparatus for selective one-step nitridation of semiconductor substrates is provided. Nitrogen is selectively incorporated in silicon regions of a semiconductor substrate having silicon regions and silicon oxide regions by use of a selective nitridation process. Nitrogen containing radicals may be directed toward the substrate by forming a nitrogen containing plasma and filtering or removing ions from the plasma, or a thermal nitridation process using selective precursors may be performed. A remote plasma generator may be coupled to a processing chamber, optionally including one or more ion filters, showerheads, and radical distributors, or an in situ plasma may be generated and one or more ion filters or shields disposed in the chamber between the plasma generation zone and the substrate support.

Method and apparatus for single step selective nitridation

A flash memory device comprises a substrate comprising silicon with a silicon dioxide layer thereon. A silicon-oxygen-nitrogen layer is on the silicon dioxide layer, and the silicon-oxygen-nitrogen layer comprises a shaped concentration level profile of oxygen through the thickness of the layer. A blocking dielectric layer is on the silicon-oxygen-nitrogen layer, and a gate electrode is on the blocking dielectric layer. Oxygen ions can be implanted into a silicon nitride layer to form the silicon-oxygen-nitrogen layer.

Modification of charge trap silicon nitride with oxygen plasma

Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process.

Enhancing NAND flash floating gate performance

Methods of forming semiconductor devices are provided herein. In some embodiments, a method of forming a semiconductor device may include providing a substrate having an oxide surface and a silicon surface; forming a nitrogen-containing layer on exposed portions of both the oxide and silicon surfaces; and oxidizing the nitrogen-containing layer to selectively remove the nitrogen-containing layer from atop the oxide surface. In some embodiments, an oxide layer is formed atop a remaining portion of the nitrogen-containing layer formed on the silicon feature. In some embodiments, the oxide surface is an exposed surface of a shallow trench isolate region (STI) disposed adjacent to one or more floating gates of a semiconductor device. In some embodiments, the silicon surface is an exposed surface of a silicon or polysilicon floating gate of a semiconductor device.

Method of selective nitridation

Growing community of inventors

Sunnyvale, CA, United States of America

Udayan Ganguly