Intel Corporation

Udaya S Natarajan

Kannappan Rajaraman

Huimin Chen

Dmitriy Berchanskiy

Vinay Raghav

Aruni P Nelson

Venkat Jayaraman

In an embodiment, a host system for selecting a power supply includes a processor, a bus interface to connect to a peripheral device, and a power controller. The power controller may be to: determine whether the processor has entered a reduced power mode; determine, via one or more bus messages, whether charging is to be performed for a battery of the peripheral device; and in response to a determination that the processor has entered the reduced power mode and that charging is not to be performed for the battery of the peripheral device, switch from a first power supply to a second power supply as an active power source of the host system. Other embodiments are described and claimed.

Selection of power supply for a host system

A power saving apparatus and method for a host system to proactively decide to save power and increase battery life when bus powered peripheral devices are connected to the System's USB TYPE-C ports. The Host (or Host System) decides if a Bus Powered Device (BPD), hub or a peripheral device requires application services, or a device-initiated wake based on wake policies of a respective Universal Serial Bus (USB) 3.2, THUNDERBOLT 3 (TBT3), USB4, DISPLAYPORT (DP) Protocol. Thereafter, the Host decides based on S0, Low Power System standby entry—wake time latency requirement along with USB TYPE-C IO Protocol policies, to trigger the system power delivery (PD) Controller to remove power to the BPD. To save power, the Host System Wake logic power partition is also powered off.

Apparatus and method to reduce standby power for systems in battery mode with a connected bus powered device

A power sequence in a power-delivery (PD) mechanism (interaction between host system components and a charger) and a firmware sequence during power contract negotiation reduces the host system power consumption at or below the pSnkStdby power limit to improve user experience and battery life. The power sequence uses USB Type-C PD protocol and timing specification to implement a synchronous trigger or interrupt and interface mechanism. The synchronous trigger or interrupt and interface mechanism between a PD controller and an embedded controller firmware controls the power consumption dynamically during the boot flow sequence to be less than or equal to pSnkStdby power limit while implementing a predictable boot sequence and optimizing boot time. The power negotiating sequence is also applicable when a source (e.g., a charger) is connected to a SoC host system which is in active state (e.g., S0) and when there is an indication of low battery capacity.

Power negotiation sequence to improve user experience and battery life

A software and hardware architecture framework utilize the specifications of Universal Serial Bus (USB) Type-C and Power Deliver (PD) to provide fine grain throttling of a processor (e.g., system-on-chip (SoC)). Based on an external charger connection or disconnection, a low latency fine grain power budget loss or gain indication to the processor is delivered. The mechanism of various embodiments is also applicable to connection or disconnection of VBUS powered peripheral devices to the system. The net power loss or gain available to the SoC and System is proportionally used to scale the processor throttling.

Low latency fine grain system-on-chip throttling apparatus and method on USB type-C port

Embodiments may include systems and methods for communication including a communication port with a first lane and a second lane, a first power controller and a second power controller coupled to the communication port. The first power controller is to control, at a first time instance, the first lane to operate in a first power state selected from a first set of power states for the first lane. The second power controller is to control, at a second time instance, the second lane to operate in a second power state selected from a second set of power states for the second lane, wherein the first power state is different from the second power state. Other embodiments may be described and/or claimed.

Power state management for lanes of a communication port

An apparatus may comprise a port to couple to a plurality of communication paths comprising a first, second, third, and fourth communication path, the communication paths each having a direction of either a receive path or a transmit path, the communication paths comprising a first communication path having a direction that may be selectively configured as a receive path or a transmit path. The apparatus further comprises a controller comprising circuitry, the controller to in response to a communication path reconfiguration command, reconfigure the direction of the first communication path such that the first communication path, second communication path, and third communication path have the same direction and the fourth communication path has a direction opposite to the direction of the first, second, and third communication paths.

Dynamic asymmetric communication path allocation

A test interface is configured to connect to a testing device and a communications device. The communications device may be configured to receive a data signal (that includes a desired data portion) from the test machine. The interface may include a data capture device and a buffer. The data capture device may be configured to receive a framing pulse signal from the communications device, to receive a framing pulse enable signal from the testing device, and to generate a reset signal in response to receiving the framing pulse signal and the framing pulse enable signal. The buffer may be configured to store the data signal from the communications device, and to clear all stored data in the buffer and store the desired data portion in response to receiving the reset signal.

Growing community of inventors

El Dorado Hills, CA, United States of America

Udaya S Natarajan