Xilinx, Inc.

Udaya Kumar Bobbili

Santosh Yachareni

Anil Kumar Kandala

Sandeep Vundavalli

Golla V S R K Prasad

Vijay Kumar Koganti

Srinivasa L Karumajji

A disclosed delay circuit includes a plurality of Schmitt triggers that are serially coupled. A first Schmitt trigger of the plurality of Schmitt triggers is configured to receive an input signal. An output control circuit is coupled to receive output signals of two or more Schmitt triggers of the plurality of Schmitt triggers, the output control circuit configured to select a signal from one of the one or more Schmitt triggers as an output signal. The output signal is a delayed version of the input signal.

Delay chain having Schmitt triggers

An interconnect element includes: a selection circuit for receiving input signals and having a selection output; a half-latch circuit having an input coupled to the selection output, wherein the half latch circuit comprises a pull-up device; and a common bias circuit coupled to the pull-up device, wherein the common bias circuit is configured to supply a tunable bias voltage to the pull-up device.

System and method to reduce footprint and improve yield of fabric muxes in programmable logic devices

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Karimnagar, India

Udaya Kumar Bobbili