Freescale Semiconductor,inc.

Intel Corporation

Intel IP Corporation

Uday Padmanabhan

Samir J Soni

Bing Xu

Vivek Bhan

Srinivasa R Bommareddy

Boris Razmyslovitch

Michael David Vicker

Richard Murphy

John R Oakley

Aniket Bharaswadkar

Koichi E Nomura

Nicholas F Jungels

Dhruv S Dani

Kenneth Edward Stebbings

Described is an apparatus which comprises: a circuitry to selectively switch between a functional clock or a scan clock; a first plurality of circuitries to generate a plurality of pulses according to the scan or functional clocks; and a second plurality of circuitries to generate a plurality of clocks according to the plurality of pulses, wherein the plurality of clocks are for testing one or more circuitries.

Apparatus and method for at-speed scan test

In accordance with the present disclosure, disadvantages and problems associated with timing accuracies of higher data rate communications systems may be reduced. In accordance with one embodiment of the present disclosure a wireless communication element comprises a first controller configured to generate data transfer information indicating a trigger value. The wireless communication element further comprises a second controller communicatively coupled to the first controller. The second controller comprises a counter configured to increment a counter value and is configured to receive the data transfer information from the first controller. The second controller is further configured to generate a data transfer trigger when the counter value corresponds with the trigger value such that the wireless communication element initiates a data transfer with a second wireless communication element in response to the data transfer trigger.

Method and system for reducing timing uncertainty of data transmission and reception

Embodiments of data recovery apparatus include oscillators, edge detection circuitry, and data storage. The oscillators generate data detection signals, which convey first series of pulses during time periods for which a serial bit stream conveys a logical 1, and second series of pulses during time periods for which the serial bit stream conveys a logical 0. The edge detection circuitry detects transition edges of the first and second series of pulses, and generates data storage signals that include first indications of detected transition edges in the first series of pulses and second indications of detected transition edges in the second series of pulses. In response to receiving a first indication, a logical 1 is written into an unmasked subset of data storage bit locations. In response to receiving a second indication, a logical 0 is written into the unmasked subset of bit locations.

Asynchronous data recovery methods and apparatus

A data recovery circuit includes a pulse width indicator circuit, an edge detection circuit and a first storage. The pulse width indicator circuit is configured to receive, at an input, a data stream and provide pulses, at respective outputs, that are indicative of respective data bits in the received data stream. The edge detection circuit is configured to receive, on respective inputs, the pulses from the pulse width indicator circuit and provide respective storage signals, on respective outputs that are indicative of a logic level of the respective data bits, responsive to the pulses. The first storage is configured to receive and store the respective storage signals.

Techniques for asynchronous data recovery

An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.

Clock circuit with clock transfer capability and method

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Chandler, AZ, United States of America

Uday Padmanabhan